From: Qingqing Zhuo <qingqing.z...@amd.com>
[Why & How]
Update DCN10 files for DCN35 usage.
Signed-off-by: Qingqing Zhuo <qingqing.z...@amd.com>
Acked-by: Harry Wentland <harry.wentl...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
.../drm/amd/display/dc/dcn10/dcn10_hubbub.h | 5 +++
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 33 +++++++++++++++++++
.../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 30 +++++++++++++++++
.../display/dc/dcn10/dcn10_stream_encoder.h | 19 +++++++++--
4 files changed, 85 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
index e8752077571a..adc876156d2e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
@@ -196,6 +196,9 @@ struct dcn_hubbub_registers {
type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C;\
type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D
+#define HUBBUB_REG_FIELD_LIST_DCN35(type) \
+ type DCHUBBUB_FGCG_REP_DIS
+
/* set field name */
#define HUBBUB_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
@@ -381,6 +384,7 @@ struct dcn_hubbub_shift {
HUBBUB_HVM_REG_FIELD_LIST(uint8_t);
HUBBUB_RET_REG_FIELD_LIST(uint8_t);
HUBBUB_REG_FIELD_LIST_DCN32(uint8_t);
+ HUBBUB_REG_FIELD_LIST_DCN35(uint8_t);
};
struct dcn_hubbub_mask {
@@ -389,6 +393,7 @@ struct dcn_hubbub_mask {
HUBBUB_HVM_REG_FIELD_LIST(uint32_t);
HUBBUB_RET_REG_FIELD_LIST(uint32_t);
HUBBUB_REG_FIELD_LIST_DCN32(uint32_t);
+ HUBBUB_REG_FIELD_LIST_DCN35(uint8_t);
};
struct dc;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index 773380ef4997..d980e6bd6c66 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -168,6 +168,8 @@ struct dcn10_link_enc_registers {
uint32_t DIO_LINKE_CNTL;
uint32_t DIO_LINKF_CNTL;
uint32_t DIG_FIFO_CTRL0;
+ uint32_t DIO_CLK_CNTL;
+ uint32_t DIG_BE_CLK_CNTL;
};
#define LE_SF(reg_name, field_name, post_fix)\
@@ -476,12 +478,42 @@ struct dcn10_link_enc_registers {
#define DCN32_LINK_ENCODER_REG_FIELD_LIST(type) \
type DIG_FIFO_OUTPUT_PIXEL_MODE
+#define DCN35_LINK_ENCODER_REG_FIELD_LIST(type) \
+ type DIG_BE_ENABLE;\
+ type DIG_RB_SWITCH_EN;\
+ type DIG_BE_MODE;\
+ type DIG_BE_CLK_EN;\
+ type DIG_BE_SOFT_RESET;\
+ type HDCP_SOFT_RESET;\
+ type DIG_BE_SYMCLK_G_CLOCK_ON;\
+ type DIG_BE_SYMCLK_G_HDCP_CLOCK_ON;\
+ type DIG_BE_SYMCLK_G_TMDS_CLOCK_ON;\
+ type DISPCLK_R_GATE_DIS;\
+ type DISPCLK_G_GATE_DIS;\
+ type REFCLK_R_GATE_DIS;\
+ type REFCLK_G_GATE_DIS;\
+ type SOCCLK_G_GATE_DIS;\
+ type SYMCLK_FE_R_GATE_DIS;\
+ type SYMCLK_FE_G_GATE_DIS;\
+ type SYMCLK_R_GATE_DIS;\
+ type SYMCLK_G_GATE_DIS;\
+ type DIO_FGCG_REP_DIS;\
+ type DISPCLK_G_HDCP_GATE_DIS;\
+ type SYMCLKA_G_HDCP_GATE_DIS;\
+ type SYMCLKB_G_HDCP_GATE_DIS;\
+ type SYMCLKC_G_HDCP_GATE_DIS;\
+ type SYMCLKD_G_HDCP_GATE_DIS;\
+ type SYMCLKE_G_HDCP_GATE_DIS;\
+ type SYMCLKF_G_HDCP_GATE_DIS;\
+ type SYMCLKG_G_HDCP_GATE_DIS
+
struct dcn10_link_enc_shift {
DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
DCN31_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
DCN32_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
+ DCN35_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
};
struct dcn10_link_enc_mask {
@@ -490,6 +522,7 @@ struct dcn10_link_enc_mask {
DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
DCN31_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
DCN32_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
+ DCN35_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
};
struct dcn10_link_encoder {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index db766689af58..aaf6c981fd9e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -189,6 +189,15 @@ struct dcn_optc_registers {
uint32_t OTG_M_CONST_DTO1;
uint32_t OTG_DRR_V_TOTAL_CHANGE;
uint32_t OTG_GLOBAL_CONTROL4;
+ uint32_t OTG_CRC0_WINDOWA_X_CONTROL_READBACK;
+ uint32_t OTG_CRC0_WINDOWA_Y_CONTROL_READBACK;
+ uint32_t OTG_CRC0_WINDOWB_X_CONTROL_READBACK;
+ uint32_t OTG_CRC0_WINDOWB_Y_CONTROL_READBACK;
+ uint32_t OTG_CRC1_WINDOWA_X_CONTROL_READBACK;
+ uint32_t OTG_CRC1_WINDOWA_Y_CONTROL_READBACK;
+ uint32_t OTG_CRC1_WINDOWB_X_CONTROL_READBACK;
+ uint32_t OTG_CRC1_WINDOWB_Y_CONTROL_READBACK;
+ uint32_t OPTC_CLOCK_CONTROL;
};
#define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
@@ -554,14 +563,35 @@ struct dcn_optc_registers {
type OTG_H_TIMING_DIV_MODE_MANUAL;
+#define TG_REG_FIELD_LIST_DCN3_5(type) \
+ type OTG_CRC0_WINDOWA_X_START_READBACK;\
+ type OTG_CRC0_WINDOWA_X_END_READBACK;\
+ type OTG_CRC0_WINDOWA_Y_START_READBACK;\
+ type OTG_CRC0_WINDOWA_Y_END_READBACK;\
+ type OTG_CRC0_WINDOWB_X_START_READBACK;\
+ type OTG_CRC0_WINDOWB_X_END_READBACK;\
+ type OTG_CRC0_WINDOWB_Y_START_READBACK;\
+ type OTG_CRC0_WINDOWB_Y_END_READBACK; \
+ type OTG_CRC1_WINDOWA_X_START_READBACK;\
+ type OTG_CRC1_WINDOWA_X_END_READBACK;\
+ type OTG_CRC1_WINDOWA_Y_START_READBACK;\
+ type OTG_CRC1_WINDOWA_Y_END_READBACK;\
+ type OTG_CRC1_WINDOWB_X_START_READBACK;\
+ type OTG_CRC1_WINDOWB_X_END_READBACK;\
+ type OTG_CRC1_WINDOWB_Y_START_READBACK;\
+ type OTG_CRC1_WINDOWB_Y_END_READBACK;\
+ type OPTC_FGCG_REP_DIS;
+
struct dcn_optc_shift {
TG_REG_FIELD_LIST(uint8_t)
TG_REG_FIELD_LIST_DCN3_2(uint8_t)
+ TG_REG_FIELD_LIST_DCN3_5(uint8_t)
};
struct dcn_optc_mask {
TG_REG_FIELD_LIST(uint32_t)
TG_REG_FIELD_LIST_DCN3_2(uint32_t)
+ TG_REG_FIELD_LIST_DCN3_5(uint32_t)
};
struct optc {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index 9d5e2a7848dd..085b269c654f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -188,6 +188,9 @@ struct dcn10_stream_enc_registers {
uint32_t HDMI_GENERIC_PACKET_CONTROL10;
uint32_t DIG_CLOCK_PATTERN;
uint32_t DIG_FIFO_CTRL0;
+ uint32_t DIG_FE_CLK_CNTL;
+ uint32_t DIG_FE_EN_CNTL;
+ uint32_t STREAM_MAPPER_CONTROL;
};
@@ -576,13 +579,25 @@ struct dcn10_stream_enc_registers {
type DIG_FIFO_RESET;\
type DIG_FIFO_RESET_DONE
+#define SE_REG_FIELD_LIST_DCN3_5_COMMON(type) \
+ type DIG_FE_CLK_EN;\
+ type DIG_FE_MODE;\
+ type DIG_FE_SOFT_RESET;\
+ type DIG_FE_ENABLE;\
+ type DIG_FE_SYMCLK_FE_G_CLOCK_ON;\
+ type DIG_FE_DISPCLK_G_CLOCK_ON;\
+ type DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON;\
+ type DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON;\
+ type DIG_FE_SOCCLK_G_AFMT_CLOCK_ON;\
+ type DIG_STREAM_LINK_TARGET
+
struct dcn10_stream_encoder_shift {
SE_REG_FIELD_LIST_DCN1_0(uint8_t);
uint8_t HDMI_ACP_SEND;
SE_REG_FIELD_LIST_DCN2_0(uint8_t);
SE_REG_FIELD_LIST_DCN3_0(uint8_t);
SE_REG_FIELD_LIST_DCN3_2(uint8_t);
-
+ SE_REG_FIELD_LIST_DCN3_5_COMMON(uint8_t);
};
struct dcn10_stream_encoder_mask {
@@ -591,7 +606,7 @@ struct dcn10_stream_encoder_mask {
SE_REG_FIELD_LIST_DCN2_0(uint32_t);
SE_REG_FIELD_LIST_DCN3_0(uint32_t);
SE_REG_FIELD_LIST_DCN3_2(uint32_t);
-
+ SE_REG_FIELD_LIST_DCN3_5_COMMON(uint32_t);
};
struct dcn10_stream_encoder {
--
2.41.0
