From: Dillon Varone <dillon.var...@amd.com> [WHY&HOW] Readback is only necessary when loaded via CPU.
Reviewed-by: Chris Park <chris.p...@amd.com> Acked-by: Hamza Mahfooz <hamza.mahf...@amd.com> Signed-off-by: Dillon Varone <dillon.var...@amd.com> --- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 8 ++++++++ drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 3 ++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index e7a50cbf2540..7a892f7bc7b0 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -142,6 +142,13 @@ enum dpia_notify_bw_alloc_status { DPIA_BW_ALLOC_CAPS_CHANGED }; +/* enum dmub_memory_access_type - memory access method */ +enum dmub_memory_access_type { + DMUB_MEMORY_ACCESS_DEFAULT, + DMUB_MEMORY_ACCESS_CPU = DMUB_MEMORY_ACCESS_DEFAULT, + DMUB_MEMORY_ACCESS_DMA +}; + /** * struct dmub_region - dmub hw memory region * @base: base address for region, must be 256 byte aligned @@ -264,6 +271,7 @@ struct dmub_srv_hw_params { bool dpia_hpd_int_enable_supported; bool disable_clock_gate; bool disallow_dispclk_dppclk_ds; + enum dmub_memory_access_type mem_access_type; }; /** diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c index 53464c3e49c1..d7d142c5b06a 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c @@ -564,7 +564,8 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, * DMCUB when backdoor loading if the write from x86 hasn't been * flushed yet. This only occurs in backdoor loading. */ - dmub_flush_buffer_mem(inst_fb); + if (params->mem_access_type == DMUB_MEMORY_ACCESS_CPU) + dmub_flush_buffer_mem(inst_fb); if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode) dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1); -- 2.41.0