[PATCH 1/6] drm/amdgpu: define ras_reset_error_count function

[Tao Zhou]

Make the code architecture more simple.

Signed-off-by: Tao Zhou <tao.zh...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  8 ++------
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c    | 17 +++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h    |  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c   |  4 ++--
 4 files changed, 23 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 31f8c3ead161..04cfd67a37a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3594,9 +3594,7 @@ static void amdgpu_device_xgmi_reset_func(struct 
work_struct *__work)
                if (adev->asic_reset_res)
                        goto fail;
 
-               if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops &&
-                   adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
-                       
adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev);
+               amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB);
        } else {
 
                task_barrier_full(&hive->tb);
@@ -5242,9 +5240,7 @@ int amdgpu_do_asic_reset(struct list_head 
*device_list_handle,
 
        if (!r && amdgpu_ras_intr_triggered()) {
                list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
-                       if (tmp_adev->mmhub.ras && 
tmp_adev->mmhub.ras->ras_block.hw_ops &&
-                           
tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
-                               
tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(tmp_adev);
+                       amdgpu_ras_reset_error_count(tmp_adev, 
AMDGPU_RAS_BLOCK__MMHUB);
                }
 
                amdgpu_ras_intr_cleared();
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 1b23651cacf4..344ebcf1a6e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1174,6 +1174,23 @@ int amdgpu_ras_query_error_status(struct amdgpu_device 
*adev,
        return ret;
 }
 
+int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
+               enum amdgpu_ras_block block)
+{
+       struct amdgpu_ras_block_object *block_obj = 
amdgpu_ras_get_ras_block(adev, block, 0);
+
+       if (!block_obj || !block_obj->hw_ops)
+               return 0;
+
+       if (!amdgpu_ras_is_supported(adev, block))
+               return 0;
+
+       if (block_obj->hw_ops->reset_ras_error_count)
+               block_obj->hw_ops->reset_ras_error_count(adev);
+
+       return 0;
+}
+
 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
                enum amdgpu_ras_block block)
 {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
index 0a5c8a107fb2..3f9ac0ab67e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
@@ -714,6 +714,8 @@ void amdgpu_ras_debugfs_create_all(struct amdgpu_device 
*adev);
 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
                struct ras_query_if *info);
 
+int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
+               enum amdgpu_ras_block block);
 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
                enum amdgpu_ras_block block);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 70e38b013309..2b7dc490ba6b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -914,7 +914,7 @@ static int amdgpu_xgmi_ras_late_init(struct amdgpu_device 
*adev, struct ras_comm
            adev->gmc.xgmi.num_physical_nodes == 0)
                return 0;
 
-       adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev);
+       amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL);
 
        return amdgpu_ras_block_late_init(adev, ras_block);
 }
@@ -1081,7 +1081,7 @@ static void amdgpu_xgmi_query_ras_error_count(struct 
amdgpu_device *adev,
                break;
        }
 
-       adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev);
+       amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL);
 
        err_data->ue_count += ue_cnt;
        err_data->ce_count += ce_cnt;
-- 
2.35.1