[PATCH AUTOSEL 6.6 33/40] drm/amd: check num of link levels when update pcie param

[Sasha Levin]

From: "Lin.Cao" <linca...@amd.com>

[ Upstream commit 406e8845356d18bdf3d3a23b347faf67706472ec ]

In SR-IOV environment, the value of pcie_table->num_of_link_levels will
be 0, and num_of_levels - 1 will cause array index out of bounds

Signed-off-by: Lin.Cao <linca...@amd.com>
Acked-by: Jingwen Chen <jingwen.ch...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Sasha Levin <sas...@kernel.org>
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 4aeb84572e5b8..5355f621388bb 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2430,6 +2430,9 @@ int smu_v13_0_update_pcie_parameters(struct smu_context 
*smu,
        uint32_t smu_pcie_arg;
        int ret, i;
 
+       if (!num_of_levels)
+               return 0;
+
        if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
                if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
                        pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];
-- 
2.42.0