[PATCH 25/35] Revert "drm/amd/display: Enable CM low mem power optimization"

[Hamza Mahfooz]

From: Gabe Teeger <gabe.tee...@amd.com>

This reverts commit c2925d905ede9f7023168857e8f488136e56a1d4.

[why]
Flickering observed. Regression search pointed to this being
the offending commit.

Reviewed-by: Charlene Liu <charlene....@amd.com>
Reviewed-by: Yihan Zhu <yihan....@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahf...@amd.com>
Signed-off-by: Gabe Teeger <gabe.tee...@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c    | 13 +++++--------
 .../amd/display/dc/resource/dcn35/dcn35_resource.c  |  2 +-
 2 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c 
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
index 1a2adb354718..994b21ed272f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
@@ -71,24 +71,21 @@ void mpc32_power_on_blnd_lut(
 {
        struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 
-/*
        if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm) {
                if (power_on) {
                        REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 
MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0);
                        REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 
MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5);
                } else if (!mpc->ctx->dc->debug.disable_mem_low_power) {
-                       //TODO: change to mpc
-                       dpp_base->ctx->dc->optimized_required = true;
-                       dpp_base->deferred_reg_writes.bits.disable_blnd_lut = 
true;
+                       ASSERT(false);
+                       /* TODO: change to mpc
+                        *  dpp_base->ctx->dc->optimized_required = true;
+                        *  dpp_base->deferred_reg_writes.bits.disable_blnd_lut 
= true;
+                        */
                }
        } else {
                REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
                                MPCC_MCM_1DLUT_MEM_PWR_FORCE, power_on == true 
? 0 : 1);
        }
-*/
-
-       REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
-                       MPCC_MCM_1DLUT_MEM_PWR_FORCE, power_on == true ? 0 : 1);
 }
 
 static enum dc_lut_mode mpc32_get_post1dlut_current(struct mpc *mpc, uint32_t 
mpcc_id)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c 
b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index 0d5a03c6d812..53eefba0b9dc 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -736,7 +736,7 @@ static const struct dc_debug_options debug_defaults_drv = {
                        .i2c = true,
                        .dmcu = false, // This is previously known to cause 
hang on S3 cycles if enabled
                        .dscl = true,
-                       .cm = true,
+                       .cm = false,
                        .mpc = true,
                        .optc = true,
                        .vpg = true,
-- 
2.42.0