Hi Heechul Yun,

Thank you for your detailed comments! It is much appreciated. It looks
like you are very close to the source of flash components for Android
phones. Indeed I had to make assumptions for lack of device
specifications, and I picked some worst case parameters based on
general published data, with a lower bound of 10,000 cycles and
assuming no support for full dynamic wear leveling where already-saved
data can be moved around to still spread the wear over the complete
storage space. Especially the latter can make a huge difference when
remaining free storage is small (or else my argument would still hold
up for a large, >= 1GB, internal MLC flash memory that is nearly
filled up). Your analysis and data may be much closer to the actual
situation with the physical Android phones that will soon hit the
market, and it is good to know that it appears to mostly refute my
earlier reliability concerns.

Thanks and best regards,

Peter


On Sep 20, 1:41 am, "[EMAIL PROTECTED]" <[EMAIL PROTECTED]>
wrote:
> Interesting discussion and very cool project.
>
> However, based on my flash experience, I think there are some
> misunderstanding to correct.
>
> First, 10000 erase cycle assumption is incorrect on the 128MB range of
> internal memory,
> because on this class of flash memory, SLC (Single Level Cell) type of
> flash memory is used and it
> typically exceeds 100000 erase cycle per block which is 10x more
> thanyour original assumption.
> 10000 erase cycle is correct for MLC technology but the size of the
> MLC flashes are at least over
> 1GB due to the production efficiency. These days, 16Gbit (say 2GB) per
> die  MLC flashes are used most
> and this will soon be replaced with 32Gbit(4GB) per die MLC flashes.
> Also, to compensate reduced endurance of MLC, flash s/w does more
> strict wear leveling technique.
> You mention the case that only 10MB free memories are available,
> however, even in this case, flash s/w keep
> track of erase count of all block (not just free block) and re-
> position the blocks so that all block can have similar
> erase count. In this way, the endurance of flash memory extends
> because the writes are evenly distribute to
> entire blocks of the flash.
>
> Second, erase time is not the order of second, but the order of
> millisecond.
> Erase only can perform per block basis which is 64KB ~ 256KB size and
> it took 1~3ms.
> Each block consist of multiple pages which is the unit of write and
> each page is 2KB or 4KB on current generation flashes.
> And each page write took 200us on SLC  and 1000us on MLC.
>
> In summary, typical NAND flash have following characteristic.
>
> SLC :
> 100000 erase per block,
> block size: 64~128KB, block erase time : 2ms
> page size. 1~2KB, page write time : 200us
>
> MLC :
> 10000 erase per block. (for 2bit per cell technology)
> block size : 128KB ~ 256KB, block erase time : 2ms
> page size :  2KB ~ 4KB, page write time : 1000us

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