2017-05-04 12:51 GMT+02:00 Luke Kenneth Casson Leighton <l...@lkcl.net>:
> > ha, bit of irony for you: gaisler research released the LEON3 SPARCv8 > core a number of years ago under the GPLv2, so that people could use > it for "academic and research purposes", the expectation being that > for "commercial" use, they would seek a license from gaisler because > you can't mix GPLv2 source with proprietary hard macro source. > > the irony / beauty is: by seeking out *specifically* hard macros even > for DDR3 that are compatible with the GPL, no proprietary license is > needed :) > > so... the source code which implements SMP cache coherency for a > multi-core LEON3... i can pull that out and use it :) > Uhhm. So your going to use the GLP'ed macro for "SMP cache coherency" from the LEON3 SPARCv8 design into the RISC-V so you can build a Multi core (SMP) RISC-V? Or are you considering a new SoC SPARC design? According to wikipedia there is also a LEON4. If it is based on the LEON3 then the source code should be available right? Or is a materialized HW design no obligated to ship with the source since it's not binary/machine code? > > l. > > _______________________________________________ > arm-netbook mailing list arm-netbook@lists.phcomp.co.uk > http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook > Send large attachments to arm-netb...@files.phcomp.co.uk >
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