Hello,
I have a question for armv7_icache_sync_range function in
sys/arch/arm/arm/cpufunc_asm_armv7.S
ENTRY(armv7_icache_sync_range)
ldr ip, .Larmv7_line_size
cmp r1, #0x8000
movcs r1, #0x8000
The register r1 is the size of range to sync.
My question is, why it is limited to 0x8000 (32K bytes) ?
Similar limitation also existed in following functions:
armv7_dcache_wb_range
armv7_idcache_wbinv_range
armv7_dcache_wbinv_range
armv7_dcache_inv_range
It's so strange!
The function armv5_ec_icache_sync_range in
sys/arch/arm/arm/cpufunc_asm_armv5_ec.S
ENTRY_NP(armv5_ec_icache_sync_range)
ldr ip, .Larmv5_ec_line_size
cmp r1, #0x4000
bcs .Larmv5_ec_icache_sync_all
It will use icache_sync_all function if size greater than 0x4000,
is this logic suitable for armv7_icache_sync_range function?
Is there any performance consideration?
Any comment?
BRs,
Joey
