Thank you for the changes. That is not something I could have managed.
Attached is the dmesg with the new kernel.
Now I need to test. I have a device on i2c1 at address 76. Is there any
sample code I can copy to read it?
-----Original Message-----
From: Artturi Alm [mailto:[email protected]]
Sent: Wednesday, September 13, 2017 1:05 PM
To: Stephen Graf <[email protected]>
Subject: Re: help with sxitwi on allwinner H3
On Wed, Sep 13, 2017 at 12:59:05PM -0700, Stephen Graf wrote:
> Thank you. I will give it a try.
>
> -----Original Message-----
> From: [email protected] [mailto:[email protected]] On Behalf
> Of Artturi Alm
> Sent: Wednesday, September 13, 2017 12:35 PM
> To: Stephen Graf <[email protected]>
> Cc: [email protected]
> Subject: Re: help with sxitwi on allwinner H3
>
> On Wed, Sep 13, 2017 at 09:23:05PM +0300, Artturi Alm wrote:
> > On Wed, Sep 13, 2017 at 10:50:28AM -0700, Stephen Graf wrote:
> > > I am trying to get an i2c driver working on orange pi one (H3).
> > > Reading the H3 datasheet would lead me to believe that the switwi
> > > driver should work. The H3 data is the same except for 2
> > > additional extended feature registers that should not be needed.
> > >
> > > I modified the dtb and the sxitwi driver to set up H3
> > > compatibility, rebuilt the kernel and got the following in the dmesg:
> > >
> > > sxitwi0 at simplebus0sxiccmu_ccu_enable: 0x0000003b
> > >
> > > iic0 at sxitwi0
> > > sxitwi1 at simplebus0sxiccmu_ccu_enable: 0x0000003c
> > >
> > > iic1 at sxitwi1
> > > sxitwi2 at simplebus0sxiccmu_ccu_enable: 0x0000003d
> > >
> > > iic2 at sxitwi2
> > >
> > > Now I am stuck trying to write some code to test the driver. I
> > > have a device on the i2c bus iic1 at address 76, a bme280
> > > temperature, pressure and humidity sensor.
> > > I am not an accomplished c programmer and would dearly like to see
> > > an example of using iic to read and write a device on the i2c bus.
> > >
> > > Note: I do not see nor can create iicx or switwi devices.
> > >
> >
> > Hi,
> >
> > after you've finished what patrick@ wrote about, you might want to
> > take a look at i/sys/dev/fdt/axp20x.c, it could very well be the
> > simplest driver on iic-bus in tree, and consequently it does attach
> > to
> > sxitwi* :)
> >
> > -Artturi
>
> So i was bored for a while; could work, but i don't have hw to test w/..
>
> -Artturi
>
>
> diff --git a/sys/dev/fdt/sxiccmu_clocks.h
> b/sys/dev/fdt/sxiccmu_clocks.h index 8b25ac42bd4..f82613e0125 100644
> --- a/sys/dev/fdt/sxiccmu_clocks.h
> +++ b/sys/dev/fdt/sxiccmu_clocks.h
> @@ -95,6 +95,10 @@ struct sxiccmu_ccu_bit sun50i_a64_gates[] = {
>
> #define H3_CLK_BUS_PIO 54
>
> +#define H3_CLK_BUS_I2C0 59
> +#define H3_CLK_BUS_I2C1 60
> +#define H3_CLK_BUS_I2C2 61
> +
> #define H3_CLK_BUS_UART0 62
> #define H3_CLK_BUS_UART1 63
> #define H3_CLK_BUS_UART2 64
> @@ -128,6 +132,9 @@ struct sxiccmu_ccu_bit sun8i_h3_gates[] = {
> [H3_CLK_BUS_OHCI2] = { 0x0060, 30 },
> [H3_CLK_BUS_OHCI3] = { 0x0060, 31 },
> [H3_CLK_BUS_PIO] = { 0x0068, 5 },
> + [H3_CLK_BUS_I2C0] = { 0x006c, 0, H3_CLK_APB2 },
> + [H3_CLK_BUS_I2C1] = { 0x006c, 1, H3_CLK_APB2 },
> + [H3_CLK_BUS_I2C2] = { 0x006c, 2, H3_CLK_APB2 },
> [H3_CLK_BUS_UART0] = { 0x006c, 16, H3_CLK_APB2 },
> [H3_CLK_BUS_UART1] = { 0x006c, 17, H3_CLK_APB2 },
> [H3_CLK_BUS_UART2] = { 0x006c, 18, H3_CLK_APB2 }, @@ -195,6 +202,10
> @@ struct sxiccmu_ccu_bit sun50i_a64_resets[] = {
>
> #define H3_RST_BUS_EPHY 39
>
> +#define H3_RST_BUS_I2C0 46
> +#define H3_RST_BUS_I2C1 47
> +#define H3_RST_BUS_I2C2 48
> +
> struct sxiccmu_ccu_bit sun8i_h3_resets[] = {
> [H3_RST_USB_PHY0] = { 0x00cc, 0 },
> [H3_RST_USB_PHY1] = { 0x00cc, 1 },
> @@ -213,4 +224,7 @@ struct sxiccmu_ccu_bit sun8i_h3_resets[] = {
> [H3_RST_BUS_OHCI2] = { 0x02c0, 30 },
> [H3_RST_BUS_OHCI3] = { 0x02c0, 31 },
> [H3_RST_BUS_EPHY] = { 0x02c8, 2 },
> + [H3_RST_BUS_I2C0] = { 0x02d8, 0 },
> + [H3_RST_BUS_I2C1] = { 0x02d8, 1 },
> + [H3_RST_BUS_I2C2] = { 0x02d8, 2 },
> };
> diff --git a/sys/dev/fdt/sxitwi.c b/sys/dev/fdt/sxitwi.c index
> 260f6f1de57..d05f67150ed 100644
> --- a/sys/dev/fdt/sxitwi.c
> +++ b/sys/dev/fdt/sxitwi.c
> @@ -178,8 +178,9 @@ sxitwi_match(struct device *parent, void *match,
> void
> *aux) {
> struct fdt_attach_args *faa = aux;
>
> - return (OF_is_compatible(faa->fa_node, "allwinner,sun4i-a10-i2c") |
> - OF_is_compatible(faa->fa_node, "allwinner,sun7i-a20-i2c"));
> + return (OF_is_compatible(faa->fa_node, "allwinner,sun4i-a10-i2c") ||
> + OF_is_compatible(faa->fa_node, "allwinner,sun7i-a20-i2c") ||
> + OF_is_compatible(faa->fa_node, "allwinner,sun6i-a31-i2c"));
> }
>
> void
>
>
I just noticed i forgot to add the call in diff below.
-Artturi
diff --git a/sys/dev/fdt/sxitwi.c b/sys/dev/fdt/sxitwi.c index
d05f67150ed..d10e6a9db5e 100644
--- a/sys/dev/fdt/sxitwi.c
+++ b/sys/dev/fdt/sxitwi.c
@@ -222,6 +222,8 @@ sxitwi_attach(struct device *parent, struct device
*self, void *aux)
/* Enable clock */
clock_enable(faa->fa_node, NULL);
+ reset_deassert_all(faa->fa_node);
+
/*
* Set clock rate to 100kHz. From the datasheet:
* For 100Khz standard speed 2Wire, CLK_N=2, CLK_M=11
OpenBSD 6.2-beta (GENERIC) #2: Wed Sep 13 13:54:17 PDT 2017
[email protected]:/usr/src/sys/arch/armv7/compile/GENERIC
real mem = 536870912 (512MB)
avail mem = 517312512 (493MB)
mainbus0 at root: Xunlong Orange Pi One
cpu0 at mainbus0: ARM Cortex-A7 r0p5 (ARMv7)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache
cortex0 at mainbus0
sxiccmu0 at mainbus0
psci0 at mainbus0
simplebus0 at mainbus0: "soc"
sxiccmu1 at simplebus0
sxipio0 at simplebus0: 94 pins
sxipio1 at simplebus0: 12 pins
sximmc0 at simplebus0
sdmmc0 at sximmc0: 4-bit, sd high-speed, mmc high-speed, dma
ehci0 at simplebus0
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 configuration 1 interface 0 "Generic EHCI root hub" rev 2.00/1.00
addr 1
ehci1 at simplebus0
usb1 at ehci1: USB revision 2.0
uhub1 at usb1 configuration 1 interface 0 "Generic EHCI root hub" rev 2.00/1.00
addr 1
sxidog0 at simplebus0
com0 at simplebus0: ns16550, no working fifo
com0: console
sxitwi0 at simplebus0
iic0 at sxitwi0
sxitwi1 at simplebus0
iic1 at sxitwi1
sxitwi2 at simplebus0
iic2 at sxitwi2
ampintc0 at simplebus0 nirq 160, ncpu 4
sxirtc0 at simplebus0
gpio0 at sxipio0: 32 pins
gpio1 at sxipio0: 32 pins
gpio2 at sxipio0: 32 pins
gpio3 at sxipio0: 32 pins
gpio4 at sxipio0: 32 pins
gpio5 at sxipio0: 32 pins
gpio6 at sxipio0: 32 pins
gpio7 at sxipio1: 32 pins
agtimer0 at mainbus0: tick rate 24000 KHz
scsibus0 at sdmmc0: 2 targets, initiator 0
sd0 at scsibus0 targ 1 lun 0: <SD/MMC, SL16G, 0080> SCSI2 0/direct removable
sd0: 15193MB, 512 bytes/sector, 31116288 sectors
uhub2 at uhub1 port 1 configuration 1 interface 0 "Terminus Technology USB 2.0
Hub" rev 2.00/1.11 addr 2
run0 at uhub2 port 2 configuration 1 interface 0 "Ralink 802.11 n WLAN" rev
2.00/1.01 addr 3
run0: MAC/BBP RT3070 (rev 0x0201), RF RT3020 (MIMO 1T1R), address
00:1f:cf:52:86:52
umass0 at uhub2 port 4 configuration 1 interface 0 "VIA Labs,Inc. USB3.0 SATA
Bridge" rev 2.10/4.14 addr 4
umass0: using SCSI over Bulk-Only
scsibus1 at umass0: 2 targets, initiator 0
sd1 at scsibus1 targ 1 lun 0: <ST310005, 28AS, CC38> SCSI4 0/direct fixed
serial.21090711000000000025
sd1: 953869MB, 512 bytes/sector, 1953525164 sectors
vscsi0 at root
scsibus2 at vscsi0: 256 targets
softraid0 at root
scsibus3 at softraid0: 256 targets
boot device: sd0
root on sd0a (1267496224926671.a) swap on sd0b dump on sd0b
