Hi, here is the diff for Allwinner H616 SoC support but work-in-progress.
Significant changes from H6:
- PMIC: AXP806 -> AXP305 (same as AXP806)
- CCU/PIO support
- SMHC(SD/MMC host)#0 and #1 needs word address for descriptor
(same as Allwinner A100), #2 needs byte address (other Allwinner
compatible)
Target board is Orange Pi Zero2 but other H616-based board might work.
Currently, RSB-connected PMIC does not work. dmesg says that:
axppmic0 at sxirsb0 addr 0x745: AXP305
sxirsb0: WR8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
I think AXP305 is working as I2C-mode (ATF turns I2C->RSB for initialize
but revert RSB->I2C when exiting), so adding a code to change RSB mode
is required.
USB is not working. A message at linux-sunxi mailing list implies
there is something errata.
https://www.mail-archive.com/linux-sunxi@googlegroups.com/msg34905.html
Allwinner H616 also has DW-APB's UART problem like H6,
cannot disable TRx FIFO. Attached diff is not contained UART fix.
dmesg:
U-Boot SPL 2021.10 (Dec 18 2021 - 15:24:36 +0900)
DRAM: 1024 MiB
Trying to boot from MMC1
NOTICE: BL31: v2.6(debug):v2.6
NOTICE: BL31: Built : 15:19:52, Dec 18 2021
NOTICE: BL31: Detected Allwinner H616 SoC (1823)
NOTICE: BL31: Found U-Boot DTB at 0x4a0821f8, model: OrangePi Zero2
INFO: ARM GICv2 driver initialized
INFO: Configuring SPC Controller
INFO: PMIC: Probing AXP305 on RSB
INFO: PMIC: aldo1 voltage: 3.300V
INFO: PMIC: aldo2 voltage: 3.300V
INFO: PMIC: aldo3 voltage: 3.300V
INFO: PMIC: bldo1 voltage: 1.800V
INFO: PMIC: dcdcd voltage: 1.500V
INFO: PMIC: dcdce voltage: 3.300V
INFO: Changed devicetree to reserve BL31 memory.
INFO: BL31: Platform setup done
INFO: BL31: Initializing runtime services
INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
INFO: BL31: cortex_a53: CPU workaround for 1530924 was applied
INFO: PSCI: Suspend is unavailable
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x4a000000
INFO: SPSR = 0x3c9
U-Boot 2021.10 (Dec 18 2021 - 15:24:36 +0900) Allwinner Technology
CPU: Allwinner H616 (SUN50I)
Model: OrangePi Zero2
I2C: ready
DRAM: 1 GiB
MMC: mmc@4020000: 0
Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1... In:
serial@5000000
Out: serial@5000000
Err: serial@5000000
Net: phy interface7
eth0: ethernet@5020000
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
Scanning disk m...@4020000.blk...
Found 3 disks
No EFI system partition
BootOrder not defined
EFI boot manager: Cannot load any image
Found EFI removable media binary efi/boot/bootaa64.efi
171127 bytes read in 11 ms (14.8 MiB/s)
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
Booting /efi\boot\bootaa64.efi
disks: sd0*
>> OpenBSD/arm64 BOOTAA64 1.7
boot> boot bsd.gdb
cannot open sd0a:/etc/random.seed: No such file or directory
booting sd0a:bsd.gdb: 9087984+1936688+579176+828456
[6798162+1363848+168+657199]=0x15c11c8
type 0x0 pa 0x40000000 va 0x40000000 pages 0x40 attr 0x8
type 0x7 pa 0x40040000 va 0x40040000 pages 0x1c0 attr 0x8
type 0x2 pa 0x40200000 va 0x40200000 pages 0x4000 attr 0x8
type 0x7 pa 0x44200000 va 0x44200000 pages 0x3cf7 attr 0x8
type 0x9 pa 0x47ef7000 va 0x47ef7000 pages 0x12 attr 0x8
type 0x7 pa 0x47f09000 va 0x47f09000 pages 0x32ee5 attr 0x8
type 0x2 pa 0x7adee000 va 0x7adee000 pages 0x7 attr 0x8
type 0x4 pa 0x7adf5000 va 0x7adf5000 pages 0x1 attr 0x8
type 0x7 pa 0x7adf6000 va 0x7adf6000 pages 0x1 attr 0x8
type 0x2 pa 0x7adf7000 va 0x7adf7000 pages 0x100 attr 0x8
type 0x1 pa 0x7aef7000 va 0x7aef7000 pages 0x2a attr 0x8
type 0x4 pa 0x7af21000 va 0x7af21000 pages 0x8 attr 0x8
type 0x6 pa 0x7af29000 va 0x596ff15000 pages 0x1 attr 0x8000000000000008
type 0x4 pa 0x7af2a000 va 0x7af2a000 pages 0x3 attr 0x8
type 0x6 pa 0x7af2d000 va 0x596ff19000 pages 0x3 attr 0x8000000000000008
type 0x4 pa 0x7af30000 va 0x7af30000 pages 0x1 attr 0x8
type 0x6 pa 0x7af31000 va 0x596ff1d000 pages 0x4 attr 0x8000000000000008
type 0x4 pa 0x7af35000 va 0x7af35000 pages 0x8 attr 0x8
type 0x2 pa 0x7af3d000 va 0x7af3d000 pages 0x5023 attr 0x8
type 0x5 pa 0x7ff60000 va 0x5974f4c000 pages 0x10 attr 0x8000000000000008
type 0x2 pa 0x7ff70000 va 0x7ff70000 pages 0x90 attr 0x8
[ using 8820536 bytes of bsd ELF symbol table ]
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
Copyright (c) 1995-2022 OpenBSD. All rights reserved. https://www.OpenBSD.org
OpenBSD 7.0-current (GENERIC.MP) #130: Mon Jan 10 08:14:46 JST 2022
u...@openbsd-current-vm.uaa.org.uk:/usr/src/sys/arch/arm64/compile/GENERIC.MP
real mem = 987348992 (941MB)
avail mem = 918302720 (875MB)
random: boothowto does not indicate good seed
mainbus0 at root: OrangePi Zero2
psci0 at mainbus0: PSCI 1.1, SMCCC 1.2
cpu0 at mainbus0 mpidr 0: ARM Cortex-A53 r0p4
cpu0: 32KB 64b/line 2-way L1 VIPT I-cache, 32KB 64b/line 4-way L1 D-cache
cpu0: 256KB 64b/line 16-way L2 cache
cpu0: CRC32,SHA2,SHA1,AES+PMULL,ASID16
cpu1 at mainbus0 mpidr 1: ARM Cortex-A53 r0p4
cpu1: 32KB 64b/line 2-way L1 VIPT I-cache, 32KB 64b/line 4-way L1 D-cache
cpu1: 256KB 64b/line 16-way L2 cache
cpu1: CRC32,SHA2,SHA1,AES+PMULL,ASID16
cpu2 at mainbus0 mpidr 2: ARM Cortex-A53 r0p4
cpu2: 32KB 64b/line 2-way L1 VIPT I-cache, 32KB 64b/line 4-way L1 D-cache
cpu2: 256KB 64b/line 16-way L2 cache
cpu2: CRC32,SHA2,SHA1,AES+PMULL,ASID16
cpu3 at mainbus0 mpidr 3: ARM Cortex-A53 r0p4
cpu3: 32KB 64b/line 2-way L1 VIPT I-cache, 32KB 64b/line 4-way L1 D-cache
cpu3: 256KB 64b/line 16-way L2 cache
cpu3: CRC32,SHA2,SHA1,AES+PMULL,ASID16
efi0 at mainbus0: UEFI 2.8
efi0: Das U-Boot rev 0x20211000
apm0 at mainbus0
"osc24M_clk" at mainbus0 not configured
"pmu" at mainbus0 not configured
agtimer0 at mainbus0: 24000 kHz
simplebus0 at mainbus0: "soc"
sxisyscon0 at simplebus0
sxiccmu0 at simplebus0
sxipio0 at simplebus0: 85 pins
ampintc0 at simplebus0 nirq 192, ncpu 4 ipi: 0, 1: "interrupt-controller"
sxiccmu1 at simplebus0
sxipio1 at simplebus0: 2 pins
sxirsb0 at simplebus0
axppmic0 at sxirsb0 addr 0x745: AXP305
sxirsb0: WR8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: WR8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: WR8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: WR8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: WR8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: WR8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: WR8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: WR8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: WR8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sximmc0 at simplebus0
sdmmc0 at sximmc0: 4-bit, sd high-speed, mmc high-speed, dma
com0 at simplebus0: DesignWare APB UART
com0: console
"spi" at simplebus0 not configured
dwxe0 at simplebus0sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: WR8 failed for run-time address 0x3a
: address 02:00:fc:bc:f9:89
rgephy0 at dwxe0 phy 1: RTL8169S/8110S/8211 PHY, rev. 6
"usb" at simplebus0 not configured
"phy" at simplebus0 not configured
ehci0 at simplebus0
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 configuration 1 interface 0 "Generic EHCI root hub" rev 2.00/1.00
addr 1
ohci0 at simplebus0: version 1.0
ehci1 at simplebus0
usb1 at ehci1: USB revision 2.0
uhub1 at usb1 configuration 1 interface 0 "Generic EHCI root hub" rev 2.00/1.00
addr 1
ohci1 at simplebus0: version 1.0
"rtc" at simplebus0 not configured
gpio0 at sxipio0: 32 pins
gpio1 at sxipio0: 32 pins
gpio2 at sxipio0: 32 pins
gpio3 at sxipio0: 32 pins
gpio4 at sxipio0: 32 pins
gpio5 at sxipio0: 32 pins
gpio6 at sxipio0: 32 pins
gpio7 at sxipio0: 32 pins
gpio8 at sxipio0: 32 pins
gpio9 at sxipio1: 32 pins
usb2 at ohci0: USB revision 1.0
uhub2 at usb2 configuration 1 interface 0 "Generic OHCI root hub" rev 1.00/1.00
addr 1
usb3 at ohci1: USB revision 1.0
uhub3 at usb3 configuration 1 interface 0 "Generic OHCI root hub" rev 1.00/1.00
addr 1
gpioleds0 at mainbus0: "power"
"vcc5v" at mainbus0 not configured
"usb1-vbus" at mainbus0 not configured
"binman" at mainbus0 not configured
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: WR8 failed for run-time address 0x3a
sxirsb0: RD8 failed for run-time address 0x3a
sxirsb0: WR8 failed for run-time address 0x3a
scsibus0 at sdmmc0: 2 targets, initiator 0
sd0 at scsibus0 targ 1 lun 0: <SD/MMC, SD16G, 0030> removable
sd0: 14768MB, 512 bytes/sector, 30244864 sectors
vscsi0 at root
scsibus1 at vscsi0: 256 targets
softraid0 at root
scsibus2 at softraid0: 256 targets
root on sd0a (75895a82bf4b7e74.a) swap on sd0b dump on sd0b
WARNING: CHECK AND RESET THE DATE!
warning: /dev/console does not exist
init: not found
panic: no init
Stopped at panic+0x160 [/usr/src/sys/kern/subr_prf.c:202]: cmp w21, #0
x0
TID PID UID PRFLAGS PFLAGS CPU COMMAND
400155 80159 0 0x14000 0x200 1 zerothread
*173123 1 0 0 0 2 swapper
db_enter() at panic+0x15c [/usr/src/sys/kern/subr_prf.c:231]
panic() at start_init+0x298 [/usr/src/sys/kern/init_main.c:734]
start_init() at proc_trampoline+0x10
https://www.openbsd.org/ddb.html describes the minimum info required in bug
reports. Insufficient info makes it difficult to find and fix bugs.
ddb{2}>
--
SASANO Takayoshi (JG1UAA) <u...@mx5.nisiq.net>
Index: dev/fdt/axppmic.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/axppmic.c,v
retrieving revision 1.13
diff -u -p -r1.13 axppmic.c
--- dev/fdt/axppmic.c 9 Jan 2022 05:42:37 -0000 1.13
+++ dev/fdt/axppmic.c 10 Jan 2022 05:28:26 -0000
@@ -292,6 +292,7 @@ struct axppmic_device axppmic_devices[]
{ "x-powers,axp209", "AXP209", axp209_regdata, axp209_sensdata },
{ "x-powers,axp221", "AXP221", axp221_regdata, axp221_sensdata },
{ "x-powers,axp223", "AXP223", axp221_regdata, axp221_sensdata },
+ { "x-powers,axp305", "AXP305", axp806_regdata },
{ "x-powers,axp803", "AXP803", axp803_regdata, axp803_sensdata },
{ "x-powers,axp805", "AXP805", axp806_regdata },
{ "x-powers,axp806", "AXP806", axp806_regdata },
@@ -492,7 +493,8 @@ axppmic_attach_common(struct axppmic_sof
sc->sc_sensdata = device->sensdata;
/* Switch AXP806 into master or slave mode. */
- if (strcmp(name, "x-powers,axp805") == 0 ||
+ if (strcmp(name, "x-powers,axp305") == 0 ||
+ strcmp(name, "x-powers,axp805") == 0 ||
strcmp(name, "x-powers,axp806") == 0) {
if (OF_getproplen(node, "x-powers,master-mode") == 0 ||
OF_getproplen(node, "x-powers,self-working-mode") == 0) {
Index: dev/fdt/ehci_fdt.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/ehci_fdt.c,v
retrieving revision 1.8
diff -u -p -r1.8 ehci_fdt.c
--- dev/fdt/ehci_fdt.c 3 Dec 2021 19:22:42 -0000 1.8
+++ dev/fdt/ehci_fdt.c 10 Jan 2022 05:28:26 -0000
@@ -175,6 +175,7 @@ struct ehci_phy ehci_phys[] = {
{ "allwinner,sun8i-r40-usb-phy", sun4i_phy_init },
{ "allwinner,sun8i-v3s-usb-phy", sun4i_phy_init },
{ "allwinner,sun50i-h6-usb-phy", sun4i_phy_init },
+ { "allwinner,sun50i-h616-usb-phy", sun4i_phy_init },
{ "allwinner,sun50i-a64-usb-phy", sun4i_phy_init },
{ "allwinner,sun9i-a80-usb-phy", sun9i_phy_init },
};
@@ -276,6 +277,7 @@ sun4i_phy_init(struct ehci_fdt_softc *sc
if (OF_is_compatible(node, "allwinner,sun8i-h3-usb-phy") ||
OF_is_compatible(node, "allwinner,sun8i-r40-usb-phy") ||
OF_is_compatible(node, "allwinner,sun50i-h6-usb-phy") ||
+ OF_is_compatible(node, "allwinner,sun50i-h616-usb-phy") ||
OF_is_compatible(node, "allwinner,sun50i-a64-usb-phy")) {
val = bus_space_read_4(sc->sc.iot, sc->sc.ioh, 0x810);
val &= ~(1 << 1);
Index: dev/fdt/sxiccmu.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxiccmu.c,v
retrieving revision 1.30
diff -u -p -r1.30 sxiccmu.c
--- dev/fdt/sxiccmu.c 3 Dec 2021 19:22:42 -0000 1.30
+++ dev/fdt/sxiccmu.c 10 Jan 2022 05:28:26 -0000
@@ -104,6 +104,9 @@ uint32_t sxiccmu_h3_r_get_frequency(stru
uint32_t sxiccmu_h6_get_frequency(struct sxiccmu_softc *, uint32_t);
int sxiccmu_h6_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
uint32_t sxiccmu_h6_r_get_frequency(struct sxiccmu_softc *, uint32_t);
+uint32_t sxiccmu_h616_get_frequency(struct sxiccmu_softc *, uint32_t);
+int sxiccmu_h616_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
+uint32_t sxiccmu_h616_r_get_frequency(struct sxiccmu_softc *, uint32_t);
uint32_t sxiccmu_r40_get_frequency(struct sxiccmu_softc *, uint32_t);
int sxiccmu_r40_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
uint32_t sxiccmu_v3s_get_frequency(struct sxiccmu_softc *, uint32_t);
@@ -149,7 +152,9 @@ sxiccmu_match(struct device *parent, voi
OF_is_compatible(node, "allwinner,sun50i-a64-r-ccu") ||
OF_is_compatible(node, "allwinner,sun50i-h5-ccu") ||
OF_is_compatible(node, "allwinner,sun50i-h6-ccu") ||
- OF_is_compatible(node, "allwinner,sun50i-h6-r-ccu"));
+ OF_is_compatible(node, "allwinner,sun50i-h6-r-ccu") ||
+ OF_is_compatible(node, "allwinner,sun50i-h616-ccu") ||
+ OF_is_compatible(node, "allwinner,sun50i-h616-r-ccu"));
}
void
@@ -276,6 +281,22 @@ sxiccmu_attach(struct device *parent, st
sc->sc_nresets = nitems(sun50i_h6_r_resets);
sc->sc_get_frequency = sxiccmu_h6_r_get_frequency;
sc->sc_set_frequency = sxiccmu_nop_set_frequency;
+ } else if (OF_is_compatible(node, "allwinner,sun50i-h616-ccu")) {
+ KASSERT(faa->fa_nreg > 0);
+ sc->sc_gates = sun50i_h616_gates;
+ sc->sc_ngates = nitems(sun50i_h616_gates);
+ sc->sc_resets = sun50i_h616_resets;
+ sc->sc_nresets = nitems(sun50i_h616_resets);
+ sc->sc_get_frequency = sxiccmu_h616_get_frequency;
+ sc->sc_set_frequency = sxiccmu_h616_set_frequency;
+ } else if (OF_is_compatible(node, "allwinner,sun50i-h616-r-ccu")) {
+ KASSERT(faa->fa_nreg > 0);
+ sc->sc_gates = sun50i_h616_r_gates;
+ sc->sc_ngates = nitems(sun50i_h616_r_gates);
+ sc->sc_resets = sun50i_h616_r_resets;
+ sc->sc_nresets = nitems(sun50i_h616_r_resets);
+ sc->sc_get_frequency = sxiccmu_h616_r_get_frequency;
+ sc->sc_set_frequency = sxiccmu_nop_set_frequency;
} else {
for (node = OF_child(node); node; node = OF_peer(node))
sxiccmu_attach_clock(sc, node, faa->fa_nreg);
@@ -1338,7 +1359,6 @@ sxiccmu_h6_get_frequency(struct sxiccmu_
case H6_CLK_APB2:
/* XXX Controlled by a MUX. */
return 24000000;
- break;
}
printf("%s: 0x%08x\n", __func__, idx);
@@ -1352,7 +1372,52 @@ sxiccmu_h6_r_get_frequency(struct sxiccm
case H6_R_CLK_APB2:
/* XXX Controlled by a MUX. */
return 24000000;
- break;
+ }
+
+ printf("%s: 0x%08x\n", __func__, idx);
+ return 0;
+}
+
+/* Allwinner H616 */
+#define H616_AHB3_CFG_REG 0x051c
+#define H616_AHB3_CLK_FACTOR_N(x) (((x) >> 8) & 0x3)
+#define H616_AHB3_CLK_FACTOR_M(x) (((x) >> 0) & 0x3)
+
+uint32_t
+sxiccmu_h616_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
+{
+ uint32_t reg, m, n;
+ uint32_t freq;
+
+ switch (idx) {
+ case H616_CLK_PLL_PERIPH0:
+ /* Not hardcoded, but recommended. */
+ return 600000000;
+ case H616_CLK_PLL_PERIPH0_2X:
+ return sxiccmu_h616_get_frequency(sc, H616_CLK_PLL_PERIPH0) * 2;
+ case H616_CLK_AHB3:
+ reg = SXIREAD4(sc, H616_AHB3_CFG_REG);
+ /* assume PLL_PERIPH0 source */
+ freq = sxiccmu_h616_get_frequency(sc, H616_CLK_PLL_PERIPH0);
+ m = H616_AHB3_CLK_FACTOR_M(reg) + 1;
+ n = 1 << H616_AHB3_CLK_FACTOR_N(reg);
+ return freq / (m * n);
+ case H616_CLK_APB2:
+ /* XXX Controlled by a MUX. */
+ return 24000000;
+ }
+
+ printf("%s: 0x%08x\n", __func__, idx);
+ return 0;
+}
+
+uint32_t
+sxiccmu_h616_r_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
+{
+ switch (idx) {
+ case H616_R_CLK_APB2:
+ /* XXX Controlled by a MUX. */
+ return 24000000;
}
printf("%s: 0x%08x\n", __func__, idx);
@@ -1732,9 +1797,8 @@ sxiccmu_h3_set_frequency(struct sxiccmu_
int
sxiccmu_h6_mmc_set_frequency(struct sxiccmu_softc *sc, bus_size_t offset,
- uint32_t freq)
+ uint32_t freq, uint32_t parent_freq)
{
- uint32_t parent_freq;
uint32_t reg, m, n;
uint32_t clk_src;
@@ -1750,8 +1814,6 @@ sxiccmu_h6_mmc_set_frequency(struct sxic
case 52000000:
n = 0, m = 0;
clk_src = H6_SMHC_CLK_SRC_SEL_PLL_PERIPH0_2X;
- parent_freq =
- sxiccmu_h6_get_frequency(sc, H6_CLK_PLL_PERIPH0_2X);
while ((parent_freq / (1 << n) / 16) > freq)
n++;
while ((parent_freq / (1 << n) / (m + 1)) > freq)
@@ -1776,13 +1838,47 @@ sxiccmu_h6_mmc_set_frequency(struct sxic
int
sxiccmu_h6_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)
{
+ uint32_t parent_freq;
+
+ parent_freq = sxiccmu_h6_get_frequency(sc, H6_CLK_PLL_PERIPH0_2X);
+
switch (idx) {
case H6_CLK_MMC0:
- return sxiccmu_h6_mmc_set_frequency(sc, H6_SMHC0_CLK_REG, freq);
+ return sxiccmu_h6_mmc_set_frequency(sc, H6_SMHC0_CLK_REG,
+ freq, parent_freq);
case H6_CLK_MMC1:
- return sxiccmu_h6_mmc_set_frequency(sc, H6_SMHC1_CLK_REG, freq);
+ return sxiccmu_h6_mmc_set_frequency(sc, H6_SMHC1_CLK_REG,
+ freq, parent_freq);
case H6_CLK_MMC2:
- return sxiccmu_h6_mmc_set_frequency(sc, H6_SMHC2_CLK_REG, freq);
+ return sxiccmu_h6_mmc_set_frequency(sc, H6_SMHC2_CLK_REG,
+ freq, parent_freq);
+ }
+
+ printf("%s: 0x%08x\n", __func__, idx);
+ return -1;
+}
+
+#define H616_SMHC0_CLK_REG 0x0830
+#define H616_SMHC1_CLK_REG 0x0834
+#define H616_SMHC2_CLK_REG 0x0838
+
+int
+sxiccmu_h616_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t
freq)
+{
+ uint32_t parent_freq;
+
+ parent_freq = sxiccmu_h616_get_frequency(sc, H616_CLK_PLL_PERIPH0_2X);
+
+ switch (idx) {
+ case H616_CLK_MMC0:
+ return sxiccmu_h6_mmc_set_frequency(sc, H616_SMHC0_CLK_REG,
+ freq, parent_freq);
+ case H616_CLK_MMC1:
+ return sxiccmu_h6_mmc_set_frequency(sc, H616_SMHC1_CLK_REG,
+ freq, parent_freq);
+ case H616_CLK_MMC2:
+ return sxiccmu_h6_mmc_set_frequency(sc, H616_SMHC2_CLK_REG,
+ freq, parent_freq);
}
printf("%s: 0x%08x\n", __func__, idx);
Index: dev/fdt/sxiccmu_clocks.h
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxiccmu_clocks.h,v
retrieving revision 1.32
diff -u -p -r1.32 sxiccmu_clocks.h
--- dev/fdt/sxiccmu_clocks.h 3 Dec 2021 19:22:43 -0000 1.32
+++ dev/fdt/sxiccmu_clocks.h 10 Jan 2022 05:28:26 -0000
@@ -468,6 +468,100 @@ struct sxiccmu_ccu_bit sun50i_h6_r_gates
[H6_R_CLK_APB2_RSB] = { 0x01bc, 0, H6_R_CLK_APB2 },
};
+/* H616 */
+
+#define H616_CLK_PLL_PERIPH0 4
+#define H616_CLK_PLL_PERIPH0_2X 5
+#define H616_CLK_AHB3 25
+#define H616_CLK_APB1 26
+#define H616_CLK_APB2 27
+#define H616_CLK_MMC0 60
+#define H616_CLK_MMC1 61
+#define H616_CLK_MMC2 62
+#define H616_CLK_BUS_MMC0 63
+#define H616_CLK_BUS_MMC1 64
+#define H616_CLK_BUS_MMC2 65
+#define H616_CLK_BUS_UART0 66
+#define H616_CLK_BUS_UART1 67
+#define H616_CLK_BUS_UART2 68
+#define H616_CLK_BUS_UART3 69
+#define H616_CLK_BUS_UART4 70
+#define H616_CLK_BUS_UART5 71
+#define H616_CLK_BUS_I2C0 72
+#define H616_CLK_BUS_I2C1 73
+#define H616_CLK_BUS_I2C2 74
+#define H616_CLK_BUS_I2C3 75
+#define H616_CLK_BUS_I2C4 76
+#define H616_CLK_BUS_EMAC0 82
+#define H616_CLK_BUS_EMAC1 83
+#define H616_CLK_USB_OHCI0 96
+#define H616_CLK_USB_PHY0 97
+#define H616_CLK_USB_OHCI1 98
+#define H616_CLK_USB_PHY1 99
+#define H616_CLK_USB_OHCI2 100
+#define H616_CLK_USB_PHY2 101
+#define H616_CLK_USB_OHCI3 102
+#define H616_CLK_USB_PHY3 103
+#define H616_CLK_BUS_OHCI0 104
+#define H616_CLK_BUS_OHCI1 105
+#define H616_CLK_BUS_OHCI2 106
+#define H616_CLK_BUS_OHCI3 107
+#define H616_CLK_BUS_EHCI0 108
+#define H616_CLK_BUS_EHCI1 109
+#define H616_CLK_BUS_EHCI2 110
+#define H616_CLK_BUS_EHCI3 111
+
+struct sxiccmu_ccu_bit sun50i_h616_gates[] = {
+ [H616_CLK_PLL_PERIPH0] = { 0x0020, 31 },
+ [H616_CLK_APB1] = { 0xffff, 0xff },
+ [H616_CLK_MMC0] = { 0x0830, 31 },
+ [H616_CLK_MMC1] = { 0x0834, 31 },
+ [H616_CLK_MMC2] = { 0x0838, 31 },
+ [H616_CLK_BUS_MMC0] = { 0x084c, 0 },
+ [H616_CLK_BUS_MMC1] = { 0x084c, 1 },
+ [H616_CLK_BUS_MMC2] = { 0x084c, 2 },
+ [H616_CLK_BUS_UART0] = { 0x090c, 0, H616_CLK_APB2 },
+ [H616_CLK_BUS_UART1] = { 0x090c, 1, H616_CLK_APB2 },
+ [H616_CLK_BUS_UART2] = { 0x090c, 2, H616_CLK_APB2 },
+ [H616_CLK_BUS_UART3] = { 0x090c, 3, H616_CLK_APB2 },
+ [H616_CLK_BUS_UART4] = { 0x090c, 4, H616_CLK_APB2 },
+ [H616_CLK_BUS_UART5] = { 0x090c, 5, H616_CLK_APB2 },
+ [H616_CLK_BUS_I2C0] = { 0x091c, 0, H616_CLK_APB2 },
+ [H616_CLK_BUS_I2C1] = { 0x091c, 1, H616_CLK_APB2 },
+ [H616_CLK_BUS_I2C2] = { 0x091c, 2, H616_CLK_APB2 },
+ [H616_CLK_BUS_I2C3] = { 0x091c, 3, H616_CLK_APB2 },
+ [H616_CLK_BUS_I2C4] = { 0x091c, 4, H616_CLK_APB2 },
+ [H616_CLK_BUS_EMAC0] = { 0x097c, 0, H616_CLK_AHB3 },
+ [H616_CLK_BUS_EMAC1] = { 0x097c, 1, H616_CLK_AHB3 },
+ [H616_CLK_USB_OHCI0] = { 0x0a70, 31 },
+ [H616_CLK_USB_PHY0] = { 0x0a70, 29 },
+ [H616_CLK_USB_OHCI1] = { 0x0a74, 31 },
+ [H616_CLK_USB_PHY1] = { 0x0a74, 29 },
+ [H616_CLK_USB_OHCI2] = { 0x0a78, 31 },
+ [H616_CLK_USB_PHY2] = { 0x0a78, 29 },
+ [H616_CLK_USB_OHCI3] = { 0x0a7c, 31 },
+ [H616_CLK_USB_PHY3] = { 0x0a7c, 29 },
+ [H616_CLK_BUS_OHCI0] = { 0x0a8c, 0 },
+ [H616_CLK_BUS_OHCI1] = { 0x0a8c, 1 },
+ [H616_CLK_BUS_OHCI2] = { 0x0a8c, 2 },
+ [H616_CLK_BUS_OHCI3] = { 0x0a8c, 3 },
+ [H616_CLK_BUS_EHCI0] = { 0x0a8c, 4 },
+ [H616_CLK_BUS_EHCI1] = { 0x0a8c, 5 },
+ [H616_CLK_BUS_EHCI2] = { 0x0a8c, 6 },
+ [H616_CLK_BUS_EHCI3] = { 0x0a8c, 7 },
+};
+
+#define H616_R_CLK_APB1 2
+#define H616_R_CLK_APB2 3
+#define H616_R_CLK_APB2_I2C 8
+#define H616_R_CLK_APB2_RSB 13
+
+struct sxiccmu_ccu_bit sun50i_h616_r_gates[] = {
+ [H616_R_CLK_APB1] = { 0xffff, 0xff },
+ [H616_R_CLK_APB2_I2C] = { 0x019c, 0, H616_R_CLK_APB2 },
+ [H616_R_CLK_APB2_RSB] = { 0x01bc, 0, H616_R_CLK_APB2 },
+};
+
/* R40 */
#define R40_CLK_PLL_PERIPH0 11
@@ -877,6 +971,76 @@ struct sxiccmu_ccu_bit sun50i_h6_resets[
struct sxiccmu_ccu_bit sun50i_h6_r_resets[] = {
[H6_R_RST_APB2_I2C] = { 0x019c, 16 },
[H6_R_RST_APB2_RSB] = { 0x01bc, 16 },
+};
+
+/* H616 */
+
+#define H616_RST_BUS_MMC0 14
+#define H616_RST_BUS_MMC1 15
+#define H616_RST_BUS_MMC2 16
+#define H616_RST_BUS_UART0 17
+#define H616_RST_BUS_UART1 18
+#define H616_RST_BUS_UART2 19
+#define H616_RST_BUS_UART3 20
+#define H616_RST_BUS_UART4 21
+#define H616_RST_BUS_UART5 22
+#define H616_RST_BUS_I2C0 23
+#define H616_RST_BUS_I2C1 24
+#define H616_RST_BUS_I2C2 25
+#define H616_RST_BUS_I2C3 26
+#define H616_RST_BUS_I2C4 27
+#define H616_RST_BUS_EMAC0 30
+#define H616_RST_BUS_EMAC1 31
+#define H616_RST_USB_PHY0 38
+#define H616_RST_USB_PHY1 39
+#define H616_RST_USB_PHY2 40
+#define H616_RST_USB_PHY3 41
+#define H616_RST_BUS_OHCI0 42
+#define H616_RST_BUS_OHCI1 43
+#define H616_RST_BUS_OHCI2 44
+#define H616_RST_BUS_OHCI3 45
+#define H616_RST_BUS_EHCI0 46
+#define H616_RST_BUS_EHCI1 47
+#define H616_RST_BUS_EHCI2 48
+#define H616_RST_BUS_EHCI3 49
+
+struct sxiccmu_ccu_bit sun50i_h616_resets[] = {
+ [H616_RST_BUS_MMC0] = { 0x084c, 16 },
+ [H616_RST_BUS_MMC1] = { 0x084c, 17 },
+ [H616_RST_BUS_MMC2] = { 0x084c, 18 },
+ [H616_RST_BUS_UART0] = { 0x090c, 16 },
+ [H616_RST_BUS_UART1] = { 0x090c, 17 },
+ [H616_RST_BUS_UART2] = { 0x090c, 18 },
+ [H616_RST_BUS_UART3] = { 0x090c, 19 },
+ [H616_RST_BUS_UART4] = { 0x090c, 20 },
+ [H616_RST_BUS_UART5] = { 0x090c, 21 },
+ [H616_RST_BUS_I2C0] = { 0x091c, 16 },
+ [H616_RST_BUS_I2C1] = { 0x091c, 17 },
+ [H616_RST_BUS_I2C2] = { 0x091c, 18 },
+ [H616_RST_BUS_I2C3] = { 0x091c, 19 },
+ [H616_RST_BUS_I2C4] = { 0x091c, 20 },
+ [H616_RST_BUS_EMAC0] = { 0x097c, 16 },
+ [H616_RST_BUS_EMAC1] = { 0x097c, 17 },
+ [H616_RST_USB_PHY0] = { 0x0a70, 30 },
+ [H616_RST_USB_PHY1] = { 0x0a74, 30 },
+ [H616_RST_USB_PHY2] = { 0x0a78, 30 },
+ [H616_RST_USB_PHY3] = { 0x0a7c, 30 },
+ [H616_RST_BUS_OHCI0] = { 0x0a8c, 16 },
+ [H616_RST_BUS_OHCI1] = { 0x0a8c, 17 },
+ [H616_RST_BUS_OHCI2] = { 0x0a8c, 18 },
+ [H616_RST_BUS_OHCI3] = { 0x0a8c, 19 },
+ [H616_RST_BUS_EHCI0] = { 0x0a8c, 20 },
+ [H616_RST_BUS_EHCI1] = { 0x0a8c, 21 },
+ [H616_RST_BUS_EHCI2] = { 0x0a8c, 22 },
+ [H616_RST_BUS_EHCI3] = { 0x0a8c, 23 },
+};
+
+#define H616_R_RST_APB2_I2C 4
+#define H616_R_RST_APB2_RSB 7
+
+struct sxiccmu_ccu_bit sun50i_h616_r_resets[] = {
+ [H616_R_RST_APB2_I2C] = { 0x019c, 16 },
+ [H616_R_RST_APB2_RSB] = { 0x01bc, 16 },
};
/* R40 */
Index: dev/fdt/sximmc.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sximmc.c,v
retrieving revision 1.12
diff -u -p -r1.12 sximmc.c
--- dev/fdt/sximmc.c 24 Oct 2021 17:52:27 -0000 1.12
+++ dev/fdt/sximmc.c 10 Jan 2022 05:28:26 -0000
@@ -205,6 +205,9 @@ struct sximmc_idma_descriptor {
#define SXIMMC_DMA_FTRGLEVEL_A20 0x20070008
#define SXIMMC_DMA_FTRGLEVEL_A80 0x200f0010
+#define SXIMMC_IDMA_ADDRSHIFT_NONE 0
+#define SXIMMC_IDMA_ADDRSHIFT_A100 2
+
int sximmc_match(struct device *, void *, void *);
void sximmc_attach(struct device *, struct device *, void *);
@@ -265,6 +268,7 @@ struct sximmc_softc {
uint32_t sc_intr_rint;
uint32_t sc_intr_mint;
uint32_t sc_idma_idst;
+ uint32_t sc_idma_addrshift;
uint32_t sc_gpio[4];
uint32_t sc_vmmc;
@@ -298,7 +302,9 @@ sximmc_match(struct device *parent, void
OF_is_compatible(faa->fa_node, "allwinner,sun7i-a20-mmc") ||
OF_is_compatible(faa->fa_node, "allwinner,sun9i-a80-mmc") ||
OF_is_compatible(faa->fa_node, "allwinner,sun50i-a64-mmc") ||
- OF_is_compatible(faa->fa_node, "allwinner,sun50i-a64-emmc"));
+ OF_is_compatible(faa->fa_node, "allwinner,sun50i-a64-emmc") ||
+ OF_is_compatible(faa->fa_node, "allwinner,sun50i-a100-mmc") ||
+ OF_is_compatible(faa->fa_node, "allwinner,sun50i-a100-emmc"));
}
int
@@ -394,6 +400,11 @@ sximmc_attach(struct device *parent, str
else
sc->sc_dma_ftrglevel = SXIMMC_DMA_FTRGLEVEL_A20;
+ if (OF_is_compatible(sc->sc_node, "allwinner,sun50i-a100-mmc"))
+ sc->sc_idma_addrshift = SXIMMC_IDMA_ADDRSHIFT_A100;
+ else
+ sc->sc_idma_addrshift = SXIMMC_IDMA_ADDRSHIFT_NONE;
+
if (sc->sc_use_dma) {
if (sximmc_idma_setup(sc) != 0) {
printf("%s: failed to setup DMA\n", self->dv_xname);
@@ -854,7 +865,7 @@ sximmc_dma_prepare(struct sximmc_softc *
bus_addr_t paddr = cmd->c_dmamap->dm_segs[seg].ds_addr;
bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len;
dma[seg].dma_buf_size = htole32(len);
- dma[seg].dma_buf_addr = htole32(paddr);
+ dma[seg].dma_buf_addr = htole32(paddr >> sc->sc_idma_addrshift);
dma[seg].dma_config = htole32(SXIMMC_IDMA_CONFIG_CH |
SXIMMC_IDMA_CONFIG_OWN);
if (seg == 0) {
@@ -871,8 +882,9 @@ sximmc_dma_prepare(struct sximmc_softc *
dma[seg].dma_config |=
htole32(SXIMMC_IDMA_CONFIG_DIC);
dma[seg].dma_next = htole32(
- desc_paddr + ((seg + 1) *
- sizeof(struct sximmc_idma_descriptor)));
+ (desc_paddr + ((seg + 1) *
+ sizeof(struct sximmc_idma_descriptor))) >>
+ sc->sc_idma_addrshift);
}
}
@@ -897,7 +909,7 @@ sximmc_dma_prepare(struct sximmc_softc *
else
val |= SXIMMC_IDST_TRANSMIT_INT;
MMC_WRITE(sc, SXIMMC_IDIE, val);
- MMC_WRITE(sc, SXIMMC_DLBA, desc_paddr);
+ MMC_WRITE(sc, SXIMMC_DLBA, desc_paddr >> sc->sc_idma_addrshift);
MMC_WRITE(sc, SXIMMC_FTRGLEVEL, sc->sc_dma_ftrglevel);
return 0;
Index: dev/fdt/sxipio.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxipio.c,v
retrieving revision 1.14
diff -u -p -r1.14 sxipio.c
--- dev/fdt/sxipio.c 24 Oct 2021 17:52:27 -0000 1.14
+++ dev/fdt/sxipio.c 10 Jan 2022 05:28:26 -0000
@@ -198,6 +198,14 @@ struct sxipio_pins sxipio_pins[] = {
"allwinner,sun50i-h6-r-pinctrl",
sun50i_h6_r_pins, nitems(sun50i_h6_r_pins)
},
+ {
+ "allwinner,sun50i-h616-pinctrl",
+ sun50i_h616_pins, nitems(sun50i_h616_pins)
+ },
+ {
+ "allwinner,sun50i-h616-r-pinctrl",
+ sun50i_h616_r_pins, nitems(sun50i_h616_r_pins)
+ },
};
int
Index: dev/fdt/sxipio_pins.h
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxipio_pins.h,v
retrieving revision 1.7
diff -u -p -r1.7 sxipio_pins.h
--- dev/fdt/sxipio_pins.h 5 Sep 2019 12:00:09 -0000 1.7
+++ dev/fdt/sxipio_pins.h 10 Jan 2022 05:28:26 -0000
@@ -9858,3 +9858,600 @@ struct sxipio_pin sun50i_h6_r_pins[] = {
{ "irq", 6 },
} },
};
+
+struct sxipio_pin sun50i_h616_pins[] = {
+ { SXIPIO_PIN(A, 0), {
+ { "emac1", 2 },
+ } },
+ { SXIPIO_PIN(A, 1), {
+ { "emac1", 2 },
+ } },
+ { SXIPIO_PIN(A, 2), {
+ { "emac1", 2 },
+ } },
+ { SXIPIO_PIN(A, 3), {
+ { "emac1", 2 },
+ } },
+ { SXIPIO_PIN(A, 4), {
+ { "emac1", 2 },
+ } },
+ { SXIPIO_PIN(A, 5), {
+ { "emac1", 2 },
+ } },
+ { SXIPIO_PIN(A, 6), {
+ { "emac1", 2 },
+ } },
+ { SXIPIO_PIN(A, 7), {
+ { "emac1", 2 },
+ } },
+ { SXIPIO_PIN(A, 8), {
+ { "emac1", 2 },
+ } },
+ { SXIPIO_PIN(A, 9), {
+ { "emac1", 2 },
+ } },
+ { SXIPIO_PIN(A, 10), {
+ { "i2c3", 2 },
+ } },
+ { SXIPIO_PIN(A, 11), {
+ { "i2c3", 2 },
+ } },
+ { SXIPIO_PIN(A, 12), {
+ { "pwm5", 2 },
+ } },
+ { SXIPIO_PIN(C, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "spi0", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "spi0", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "spi0", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "spi0", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 6), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 7), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "spi0", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 8), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 9), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 10), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 11), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 12), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 13), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 14), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 15), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "spi0", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 16), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "spi0", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(F, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "jtag", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(F, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "jtag", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(F, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "uart0", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(F, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "jtag", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(F, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "uart0", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(F, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "jtag", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(F, 6), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 6), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart1", 2 },
+ { "jtag", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 7), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart1", 2 },
+ { "jtag", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 8), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart1", 2 },
+ { "clock", 3 },
+ { "jtag", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 9), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart1", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 10), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2s2", 2 },
+ { "clock", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 11), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2s2", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 12), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2s2", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 13), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2s2", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 14), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2s2", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 15), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "i2c4", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 16), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "i2c4", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 17), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "i2c3", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 18), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "i2c3", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 19), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "pwm1", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart0", 2 },
+ { "pwm3", 4 },
+ { "i2c1", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart0", 2 },
+ { "pwm4", 4 },
+ { "i2c1", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart5", 2 },
+ { "spdif", 3 },
+ { "pwm2", 4 },
+ { "i2c2", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart5", 2 },
+ { "pwm1", 4 },
+ { "i2c2", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "spdif", 3 },
+ { "i2c3", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "i2s3", 3 },
+ { "spi1", 4 },
+ { "i2c3", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 6), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "i2s3", 3 },
+ { "spi1", 4 },
+ { "i2c4", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 7), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "i2s3", 3 },
+ { "spi1", 4 },
+ { "i2c4", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 8), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "i2s3_dout0", 3 },
+ { "spi1", 4 },
+ { "i2s3_din1", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 9), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2s3_din0", 3 },
+ { "spi1", 4 },
+ { "i2s3_dout1", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 10), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "ir_rx", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "dmic", 3 },
+ { "i2s0", 4 },
+ { "hdmi", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "dmic", 3 },
+ { "i2s0", 4 },
+ { "hdmi", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "dmic", 3 },
+ { "i2s0", 4 },
+ { "hdmi", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "dmic", 3 },
+ { "i2s0_dout0", 4 },
+ { "i2s0_din1", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "dmic", 3 },
+ { "i2s0_din0", 4 },
+ { "i2s0_dout1", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart2", 3 },
+ { "ts0", 4 },
+ { "i2c0", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 6), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart2", 3 },
+ { "ts0", 4 },
+ { "i2c0", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 7), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart2", 3 },
+ { "ts0", 4 },
+ { "i2c1", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 8), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart2", 3 },
+ { "ts0", 4 },
+ { "i2c1", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 9), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart3", 3 },
+ { "ts0", 4 },
+ { "i2c2", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 10), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart3", 3 },
+ { "ts0", 4 },
+ { "i2c2", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 11), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart3", 3 },
+ { "ts0", 4 },
+ { "pwm1", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 12), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart3", 3 },
+ { "ts0", 4 },
+ { "pwm2", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 13), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart4", 3 },
+ { "ts0", 4 },
+ { "pwm3", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 14), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart4", 3 },
+ { "ts0", 4 },
+ { "pwm4", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 15), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart4", 3 },
+ { "ts0", 4 },
+ { "clock", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 16), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart4", 3 },
+ { "ts0", 4 },
+ { "clock", 5 },
+ { "irq", 6 },
+ } },
+};
+
+struct sxipio_pin sun50i_h616_r_pins[] = {
+ { SXIPIO_PIN(L, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "s_rsb", 2 },
+ { "s_i2c", 3 },
+ } },
+ { SXIPIO_PIN(L, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "s_rsb", 2 },
+ { "s_i2c", 3 },
+ } },
+};
Index: dev/fdt/sxisyscon.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxisyscon.c,v
retrieving revision 1.2
diff -u -p -r1.2 sxisyscon.c
--- dev/fdt/sxisyscon.c 24 Oct 2021 17:52:27 -0000 1.2
+++ dev/fdt/sxisyscon.c 10 Jan 2022 05:28:26 -0000
@@ -52,7 +52,8 @@ sxisyscon_match(struct device *parent, v
if (OF_is_compatible(node, "allwinner,sun8i-h3-system-control") ||
OF_is_compatible(node, "allwinner,sun50i-a64-system-control") ||
OF_is_compatible(node, "allwinner,sun50i-h5-system-control") ||
- OF_is_compatible(node, "allwinner,sun50i-h6-system-control"))
+ OF_is_compatible(node, "allwinner,sun50i-h6-system-control") ||
+ OF_is_compatible(node, "allwinner,sun50i-h616-system-control"))
return 10; /* Must beat syscon(4). */
return 0;
