Hi, Florent and I got the full DDR3 SODIMM to work on the KC705 board. The peak bandwidth is 64Gbps, which I think sets the record of the fastest open source SDRAM controller :) Please test on yours and report your results - all the code is committed in MiSoC, so you should be able to build and flash everything with: ./make.py -t kc705 -Op toolchain ise all (Vivado should work too, but I've done more limited testing)
The main change compared to the existing DDR/DDR2 support in MiSoC is the write leveling and read calibration mechanism. The first step in the calibration algorithm is write leveling. Its main purpose is to align DQS with the clock in order to meet the DQS/CK timing specification of the SDRAM in the presence of clock skew (that increases - significantly - from one SDRAM chip to the next due to the DDR3 fly-by topology). The BIOS puts the SDRAM into a special mode that makes it sample CK asynchronously with DQS and report the sampled value on DQ. When leveling a SDRAM chip that has a small amount of skew, and with CK and DQS launched at the same time on the FPGA, the sampled CK value is 0 as CK is more loaded (and therefore delayed) than DQS. The BIOS then progressively increases the delay on DQS until the SDRAM returns 1; at this time, DQS and CK are aligned and leveling proceeds to the next chip. The SODIMM modules actually have a lot of skew and the last SDRAM chips have a little more than one bit time of delay. For those, we assume that the delay is less than two bit times, and we can detect them by their sampling of CK=1 during leveling with no DQS delay. The BIOS first places them into the CK=0 sampling region by delaying DQS, and then keeps delaying DQS until CK=1 is sampled again. The write delay on the data lines is set to the write leveling DQS delay minus half a bit time to meet the DQS/DQ setup/hold requirements. At this point, we have functional writes to the SDRAM. The BIOS then proceeds to the rough read timing calibration. In this step, it takes the SDRAM chips that have the most skew (as detected from the write leveling) and issues a bitslip operation to the read SERDES to make it sample the data one bit time earlier. This ensures that the later application of the IDELAY can align the read data burst with the system clock. Finally, for the fine read timing calibration, the BIOS writes a pseudo-random sequence to the SDRAM, and reads it back and verifies it repeatedly while scanning the IDELAY values for each SDRAM chip. It then places each IDELAY value in the middle of its working range. After those steps, the DDR3 is ready for normal operation. Sébastien _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
