> Does the FPGA need to generate one pulse per DAC sample? Yes, one pulse is required per sample. One way of doing this might be to have a fixed frequency clock that is gated by a RTIO channel.
On Wed, Jan 21, 2015 at 7:46 PM, Sébastien Bourdeauducq <s...@m-labs.hk> wrote: > On 01/22/2015 02:08 AM, Joe Britton wrote: > > * The "waveform advance" pulse to the 6733 is what causes its output to > > transition from one ADC channel (voltage) to another. We usually > > generate this pulse from the FPGA not from a periodic clock (eg crystal > > oscillator). This makes it possible to a) conserve memory on the 6733 > > when a static output is desired and b) reduce noise on the 6733 analog > > outputs (its more noisy when being clocked). > > Does the FPGA need to generate one pulse per DAC sample? > > Sébastien > > _______________________________________________ > ARTIQ mailing list > https://ssl.serverraum.org/lists/listinfo/artiq >
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