Sometime in 2015 I'm aiming for an extension to ARTIQ for low-latency, high-bandwidth optical interconnect for ARTIQ peripherals. This underpins several applications. For example,
* streamlined real-time control of lab peripherals used by trapped-ion and neutral atom AMO groups; "real-time" means latency much lower than qubit coherence time * all-digital, closed-loop PID loops spanning devices distributed around a lab; requires deterministic (<< 1ns jitter), low-latency (<100 ns), Gigabit-bandwidth links * break ground loops for laboratory peripherals; use commodity Gigabit optical links * clock and control synchronization for distributed quantum systems (e.g. quantum networking, quantum-enabled sensors) When planning for this so-called Distributed Real-Time I/O (DRTIO) upgrade to ARTIQ it's necessary to answer the question "What type of clock stability is needed by trapped ion experiments?" Here's my go at it. ------- # Trapped Ion Qubit Timing & Clock Requirements ## Ramsey for qubit Here's a physics example that illustrates the type of clock stability that a trapped ion qubit experiment would require. Do a 1 second long Ramsey interference experiment on a 10 GHz qubit. This involves a pair of short microwave pulses separated in time by 1 second. The microwave source is locked to a low phase noise reference oscillator. If the integrated phase error on the 10 GHz between the two pulses is pi Radians the atomic coherence is lost. To ensure that oscillator phase noise is not the limiting factor aim for a phase error of less than pi/10 over 1 second, a stability of 1e-11 is needed. A spin-echo sequence will give insensitivity to slow (<1 Hz) variations in reference oscillator frequency at the 1e-11 level. ## Ramsey for clock/sensing If the aim is to use the Ramey-type experiment to sense B-field (or local oscillator) drift, greater stability is required to beat down quantum projection noise. One hundred repetitions of the 1 s Ramsey experiment would require 1e-13 reference oscillator stability. This level of stability is straighforward when a high quality reference oscillator is co-located with the 10 GHz microwave source. ## Adiabatic trapped ion transport Another physics example is the timing requirements for DACs used to define the harmonic trapping potential of trapped atomic ions. For non-adiabatic transport of ions it's useful to have a DAC update (~100 MHz) rate that is much higher than the ions secular motion (~1 MHz). In this case a 1 ns jitter seems adequate relative to 1/100MHz. As a more stringent requirement, we might require that ion motional heating following diabatic transport be delta_n << 0.1 quanta. As a worst-case limit use expression (2) in Ref [1]. Assume, ' 9Be+ ion, v = 1mm/10us, fCOM = 1 MHz and t = 10 us + epsilon.' epsilon | delta_n --------------|---------- 1e-9 s | 0.11 0.1e-9 s | 0.001 Therefore, by this metric we desire << 1 ns jitter. 100 ps deviation over 10 us would be adequate. There are experiments I could imagine that would require at or below 100 ps deviation over intervals as long as 1 ms. ## Proposed DRTIO target What should be target for DRTIO? Jitter below 100 ps should be adequate for DRTIO devices responsible for ion transport. And, a wide variety of ADC applications. If DRTIO devices are to be used for distributed Ramsey experiments this requires much lower jitter (< 10 ps) and places additional demands on the stability of remote oscillators. Initially, I'd say it's OK if DRTIO aims shoot for the first criterion. Sound good? ------- # DRTIO work plan With these performance criteria and the demonstrated performance of White Rabbit in mind [2], here's a proposed work plan for bringing DRTIO to ARTIQ. **Step 1)** KC705 to KC705 loopback test over SMA cables **Step 2)** KC705 to KC705 loopback test with SFP (single-mode bi-directional fiber link for Rx/Tx) **Step 3)** Two KC705 linked by SFP, 10 m fiber **Step 4)** Integrate DRTIO link into ARTIQ's RTIO core **Step 5)** Demonstrate DRTIO using one KC705 as Core Device (and master clock) and second KC705 as Satellite. Link is DRTIO over fiber. Satellite implements 32 channel TTL PHYs. Test that Objectives 3,4,5 are met using TTL PHY on Satellite and TTL PHY on Core Device. For each Step demonstrate that Objectives 1 to 5 can be met. **Objective 0**... Deterministic pseudo-random data generator; e.g. 64-bit counter scrambled by something like SHA1 **Objective 1**... Recovery of 100 MHz clock from serial link; clock recovery sufficient for sustained data transmission at 1 Gbps **Objective 2**... Demonstration of 1 Gbps transmission with error rate 1e-14, 1 Gbps over one day of running **Objective 3**... Comparison of two synchronized KC705 100 MHz clocks: RMS jitter <5 ps over periods of 1 ms and 1s; maximum peak to peak skew < 20 ps over 1 second **Objective 4**... Round-trip determinacy: <10 ns jitter in round-trip, over 1 minute observation period (1 m cable length) **Objective 5**... Round-trip latency <200 ns (including all latencies: FPGA logic, FPGA Transceivers, SFP; excluding fiber propagation), over 1 second observation period (1 m cable length) Please comment. Some will be delighted if we used markdown on mailing list discussions. See the following markdown editor http://dillinger.io/ -Joe # References [1] R. Bowler, et al, "Coherent diabatic ion transport and separation in multizone trap array", PRL 109, 080502 (2012) [2] G. Daniluk, T. Wlostowski "White Rabbit: Sub-Nanosecond Synchronization for Embedded Systems" http://www.clepsydratime.com/file_upl/PDF/WhitePapers/Elproma%20CERN%20%28White_Rabbit%29.pdf _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
