>The current circuitry will add several hundred ps of peak-to-peak jitter at a >minimum. > This is more reasonable if you are talking about a signal that stays on just > one > board, but again you will need to do some careful engineering.
It's worse than that. In June I tested the legacy (circa 2004) LVDS bus to 50-Ohm driver we use in the Penning lab and found that it fails to reproduce a 50% duty cycle square wave >20 MHz. Continued use of this legacy front-end to the experiment is my lazy approach to getting ARTIQ to work with the KC705 and is certainly not the path forward. My point in this email thread is to establish the timing capabilities of the FPGA itself. If a lab wants to take advantage, additional work is needed to couple to their apparatus. COTS solutions exist for low jitter optical links. For example, SFP+ transceivers achieve > 10 Gbps. -Joe _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
