Hi,
On Friday, February 19, 2016 01:45 AM, Slichter, Daniel H. wrote:
I haven't been able to test the clock generator (to look for phase
slippage) because I can't get a signal from either the ClockGen pin
AFAICT you are using the ClockGen correctly. Have you double-checked the
gateware source and the pin assignments? The gateware needs to have a
ttl_simple.ClockGen PHY on that channel, which is not compatible with
the other TTL commands.
For testing phase, you can also generate a clock from the CPU this way:
while True:
self.ttl.pulse(1*us)
delay(1*us)
or any of the pins configured as InOut pins (in the bitstream and
device_db).
I guess the problem comes from this: TTLInOut is in input (Hi-Z) mode by
default. You need to call self.ttlX.output(), and then add a delay of at
least 8ns before issuing any other commands on the same channel.
Typically, the startup kernel would need to issue output() calls for
those TTLInOut channels that are always used as outputs in a given setup
(the output and other RTIO PHY states are kept between kernels).
The reasons for this design are:
1) preventing the contention that could occur if they were in output
(driving) mode by default.
2) on()/off()/pulse() do not implicitly set a channel as output so that
all the transitions are the same electrically (no difference between the
first transition that would be Hi-Z -> new level and the the subsequent
ones that would be old level -> new level).
Sebastien
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