On Fri, Sep 30, 2016 at 1:18 PM, Sébastien Bourdeauducq <s...@m-labs.hk> wrote: > Here is a plan for clocking the Sinara system. Please comment.
Sounds good. This is the layout that we discussed in Warsaw with the addition of the coarse and fine delay. Using the coarse alignment and the delays is a to get rid of the sample shuffling is nice. > measure its phase with a high precision. It then derives a phase correction > value that it programs into the relevant registers of the clock chip to > delay SYSREF by the duration that aligns it with the RTIO clock. Not only the SYSREF but also all the slower deviceclocks (FPGA, ADCs) need shifting. > Sayma RTM clock chip connections > -------------------------------- > > The HMC7044 has 14 outputs. We should use them for: > * DAC clocks, x2 > * DAC SYSREF, x2 [with fine delay] > * ADC clocks, x2 > * ADC SYSREF, x2 [with fine delay] > * FPGA SYSREF > * FPGA MGT reference clock for DAC > * FPGA MGT reference clock for ADC > * additional outputs to FPGA, usable e.g. if we have problems with the > recovered RTIO clock. I'd firmly assign another SYSREF to the FPGA. The ADC and the DAC clocking might not ed up using the same SYSREF. -- Robert Jördens. _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
