Hi,
On Wednesday, October 05, 2016 12:17 PM, Cornelius Hempel wrote:
At this stage, we are just trying to get an understanding of the size and
functional requirements (FPGA space and features) at the verilog level - which
both Trung, our FPGA engineer, and Moglabs speak.
you can simply look at the synthesis logs on our buildserver, e.g.
http://buildbot.m-labs.hk/builders/artiq-board/builds/66/steps/conda_build/logs/stdio
http://buildbot.m-labs.hk/waterfall?show=artiq-board
Note that most of our builds are for the KC705, which uses significantly
more resources than the Pipistrello target.
Sébastien
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