# Phaser2 Progrss Report for November 2016 This reports summarizes the progress of the multi channel two tone arbitrary waveform generator project. It builds on the "phaser" project which previously demonstrated a RTIO compatible, multi channel, GHz data rate DDS (https://ssl.serverraum.org/lists-archive/artiq/2016-October/001021.html). Over the coming months "phaser" will evolve into the Sayma device which is part of the upcoming Sinara family (https://github.com/m-labs/sinara).
## Smart Arbitrary Waveform Generator Channels The SAWG channels are versatile and flexible parametrizations of wideband signals commonly encountered in Quantum Physics labs. The parametrization is described in the artiq-hardware whitepaper (https://github.com/m-labs/artiq-hardware). The SAWG channels have been constructed and tested in functional simulations and unittests. Different approaches to the clocking of the data path and the parallelization and pipelining of the sample streams were explored. The datapath is able to generate one batch of up to 8 samples every 4 ns. Latency is dominated by JESD204B link latency and CORDIC latency. The group delay of the RTIO channels to the DAC output is matched using delay lines. A generic RTIO spline interpolator was written and implemented. The interpolators are used as data sources for frequency, phase, amplitude and DC offset for the SAWG channels. Regular speed (one sample per FPGA clock cycle) a,f,p-interpolating DDS cores were implemented enabling two-tone output. Initial RTIO spline data support for kernel and runtime was added. The design was adapted to 300 MHz data rate, 1x interpolation and mix mode to cover the second and third Nyquist zones at 150-300 MHz and 300-450 MHz respectively. The original prototyping and proof-of-concept code which was previously used to demonstrate gateware capable of generating sample streams at GHz data rate was published at https://github.com/m-labs/phaser. ## Ultrascale support Ultrascale devices have a different JTAG interface and SPI flash architecture for retrieving bitstreams and data than previous 7 series or spartan devices. Initial support for the ultrascale boundary scan primitives has been added to the proxy bitstreams for openocd. Similarly, initial support for the two flash devices connected to ultrascale chips was developed. ## DRTIO We have developed a basic implementation of DRTIO: the link layer, clock syntonization, real-time packet processing and remote output FIFO management, and support for auxiliary low-priority packets. We are currently running it on a pair of KC705s connected with GbE SFPs and fiber, and the master KC705 can successfully issue RTIO writes to TTLs on the satellite. The next steps include support for wider output data (to support remote phasers with GSPS DACs), multiple links on the master, RTIO inputs, higher bandwidth (4Gbps), and using Kintex Ultrascale transceivers. For the ARTIQ team, -- Robert Jördens. _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
