We're in the final stretch of Sinara schematic review (0.1rc) and ready to tackle Sinara layout review (0.1). On the current timeline, testing of v0.1 prototype hardware will commence in Jan 2017. For those on the mailing list please note that most of the discussion is taking place in the form of github Issues. Design files are in the repository.
https://github.com/m-labs/sinara/issues https://github.com/m-labs/sinara/ Here's my view on Issues outstanding. https://github.com/m-labs/sinara/projects/6 Prospective users of the Sinara system may like to weigh in on design of the Kasli PCB (led by M-Labs) and on IO breakout from Metlino/Kasli (led by Warsaw Technical University). https://github.com/m-labs/sinara/issues/129 https://github.com/m-labs/sinara/issues/99 Ping @jordens to join the Sinara project on github. https://github.com/jordens -Joe ------- Joe Britton Sensors and Electron Devices Army Research Lab 2800 Powder Mill Rd Adelphi, MD 20783 301-394-3130 joseph.w.britton5....@mail.mil _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
