On Saturday, December 17, 2016 12:02 PM, Sébastien Bourdeauducq via
ARTIQ wrote:
Before DRTIO can operate, the clock chip (HMC* on Sayma and AD9516 on
KC705) needs to be running.
Strictly speaking: this is needed only for the two-KC705 system. But we
might as well use the same scheme everywhere, and it avoids the corner
case of operating the kernel CPU with no RTIO clock running.
The generic chip configuration code should go in firmware/libbsp.
With the RTM FPGA, SPI will have to go over the SERDES link. I'm still
thinking about a generic "I/O expander" similar to mini-DRTIO; we can
have half-rate, quarter-rate, etc. updates for some pins in order to
save bandwidth.
Sébastien
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