On Wed, Jul 18, 2018 at 5:48 PM Thomas Harty via ARTIQ <artiq@lists.m-labs.hk> wrote: > > * Is (f0+f1, f0+f2) better than (f0+f1-f2, f0+f1+f2)? (with f0 coarse, > > and f1/f2 fine) etc. Or other parametrizations. > > * What is the maximum step size of f0 in terms of the f1/f2 rate? > > By `(f0 + f1)` do you mean the current parametrization? > http://m-labs.hk/artiq/manual-master/core_drivers_reference.html?highlight=sawg#artiq.coredevice.sawg.SAWG
Yes. > My minimal requirements are to be able to pick an arbitrary (within the SAWG > BW) centre frequency, fc, and to be able to produce either a single tone or a > pare of tones anywhere within, say, +-10MHz of that centre frequency without > changing the DUC frequency f0. So long as the DUC size steps are small enough > to allow this then I'm happy. The proposal is to have the f0 DUC at 125 MHz or 62.5 MHz granularity and do move the remaining center frequency offset into f1/f2 > Having said that, more flexibility is always useful, so I'd be keen to keep > the f0 size steps as small as reasonably (without excessive complexity) > possible. I don't understand the flexibility v complexity trade-offs well > enough here to know what level of flexibility would be best to shoot for. The coarse f0 DUC (as per the proposal) would be tens of multipliers instead of eight CORDICs+accumulators. We'd need an exploratory project to get hard numbers for the resource trade of. > > * What width is really needed for the FTW on f1/f2? > > Less than 32-bits (0.2Hz for 1GSPS) is problematic. A few more bits would be > nice, but can be traded off against gateware complexity. One eighth of that. f1/f2 would run at 125 MHz. > > * What width do we need for the CORDICs (IQ)? Are we just beating the > > spurs? Then we certainly don't need 16 bits. Or is 16 bit amplitude > > resolution needed? > > And saying "one LSB", "16 bit" or equivalent might sound convenient > > but it's also potentially very expensive. If the requirement can't be > > derived from physics, then something like the DAC SFDR would be a > > reasonable target. > > Remind me, does the CORDIC width affect broad-band noise, or just spur level? > If it's just spurs then I'm probably not too concerned so long as it doesn't > degrade the SFDR -- although, I'd need to look at where the spurs are to be > confident in that. Both in different ways through different "width" paramters. What broad band phase noise is required? Robert. _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
