ASIC Verification engineers in San Jose/bay area..
MOI: Phone/Skype
No H1-b please
*Skill set:*
· Verilog and C/C++ coding a must
· Makefiles, Perl scripting a must
· Chip/full system level ASIC Verification skills, and debug skills
a must
o Debug using waveforms a must, Verdi source level debug a plus
· Board level debug with logic analyzers, scopes desirable
· Experience working with AMD 64 architecture a great plus
· Experience working with PCI-Express a plus
· System level knowledge a must
o System is defined as a test bench containing {CPU + GPU + multi-media
engines + Southbridge} with hardware based coherency, hardware based
transaction ordering
o System could be a simulation test bench, emulation test bench or a
board
o System level knowledge/verification does *not* mean signal integrity
checking, electrical checks, EMC checks, thermal checks, ATPG testing on a
board, DFT/DFx testing, static timing analysis, lint checking
o Tests will be written in C/C++, compiled for CPU and will be run on
simulation/emulation/board unchanged
· Block/unit level verification skills using OVM/UVM knowledge
desirable (not required for the work, but having this knowledge means the
candidate has been working on verification in the recent past).
*Regards, Meenu Yadav*
*IT-Technical Recruiter Source Infotech Inc. **3840 Park Avenue, Suite
C-205, Edison, NJ-08820*
*Phone#: 609-608-0466|| Fax: 732-909-2282 || Email: *
*mya...@sourceinfotech.com* <mya...@sourceinfotech.com>
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