On Mon, 8 Aug 2011 10:35:00 -0500, Mark Hammack wrote: >Ex: > >R1 EQU 1,,,,,GR31 >RW1 EQU 1,,,,,GR64 >... > >PTR DS AD >... > > L R1,PTR <= hoped this would generate a >warning but it didn't
I assume you meant: R1 EQU 1,,,,GR32 since EQU only accepts 5 operands and GR31 is not valid but GR32 is. There is no reason why this should generate a warning. The register type of R1 is GR32 which agrees with what the first operand of the L instruction. Now if what you want is for HLASM to flag use of the L instruction when the second operand is not a fullword, then I would expect a great many programs to generate errors. It is very common to intentionally load part of a a doubleword using the L instruction. >Now for the real question. When I coded: > > LMH RW1,RW1,=F'0' > >I got a warning about incompatible registers which seems odd. Since LMH >sets the high order fullword of a 64 bit register(s), I would think the >TYPECHECK would accept this notation and complain if I had specified the 31 >bit registers. Likely this is yet another example of a register specification bug in HLASM. If you are current on HLASM maintenance, then report it to IBM. It seems like they are constantly fixing these. And I doubt they will ever fix the problems with modal instructions such as LA where the assembler can't know how many register bits will be changed. >Is anyone using TYPECHECK to successfully catch issues earlier in the >process? I gave up years ago. TYPECHECK(REGISTER) is great for catching some coding errors but between the GR32 vs. GR64 errors in the HLASM operation code tables and the modal operands, I just use GR - not GR32 or GR64. David Bond
