On 5/24/2012 9:35 AM, Jon Perryman wrote:
Has anyone from IBM endorsed this? POP's doesn't state that the PSW is
decremented to cause re-execution of the instruction.
Thanks, Jon.
Why would the PSW need to be decremented?
The POO says:
The execution of the instruction is interruptible. When
an interruption occurs, other than one that follows termination,
the lengths in general registers R1 + 1 and
R2 + 1 are decremented by the number of bytes
moved, and the addresses in general registers R1
and R2 are incremented by the same number, so that
the instruction, when reexecuted, resumes at the
point of interruption.
-------------
What you seem to be missing is that the 'reexecution'
is done automatically: your program cannot detect it,
unlike instructions that process a 'cpu-determined
number of bytes' and then set the condition code for
you to check.
But interruptible instructions work so that your code
does not need to do anything about handling interrupts
or resuming execution. I've used the instruction in
lots of places and it works that way.
________________________________
From: Paul Gilmartin<paulgboul...@aim.com>
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sent: Wed, May 23, 2012 9:37:23 PM
Subject: Re: MVC with 2nd operand length
On May 23, 2012, at 22:27, Jon Perryman wrote:
MVCL is an instruction begging for a macro. Besides loading registers and
destroying the contents of 4 registers upon completion, it is also
interruptible
so you have to ensure the move is complete.
Ensuring the move is complete is handled by the hardware.
-- gil
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