From: Bernd Oppolzer Sent: Sunday, 17 February 2013 8:03 PM
I'd like to second that, for some reasons:
a) other machines like RS/6000 etc borrowed the RR/RX/RS instruction set from the S/370, and they are RISC in my opinion
Not really; see previous email regarding what constitutes a RISC instruction.
b) I know other machines (old German mainframes) which are definitely CISC, and they have stack instructions or they are able to modify other instructions by combining them with stack instructions and replacing the address part of the instructions by register references and all such things - that is really complicated - compared to that, the S/370 instruction set is very simple. You can do very much with only one instruction of the TR 440 mainframe ... increment a register, store into a memory location ... all in one combined instruction, which you can compose of two simple instructions etc.
The S/360 can increment a memory location (via AP, for example), but not using an RX instruction, of course. Would have been useful to have one. But with TR, TRT, ED. EDMK, PACK. UNPK, etc, etc, etc, you can do a lot with one instruction.
c) think of the pipelining efforts the modern z processors do - that's RISC - up to ten instructions executing in parallel
The ability to run instructions in parallel doesn't imply RISC.
As Tony said: the complex instructions like EDMK only count for a very small percentage in the executed instructions summary.
See earlier email pointing out that a weighted frequency count gives more meaningful comparisons.
The mainframe, in fact, is both: a very fast RISC processor,
It isn't. Most of the instructions are CISC-type.
and a decimal machine, doing commercial workload at a reasonable speed.
