1. I would suggest your LG G1,50(,G1) should rather be AGHI G1,50
2. LLGTR loads 31 bits, therefore the high-order word is zeroed. Remove it.

-----Original Message-----
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU]
On Behalf Of esst...@juno.com
Sent: 28 August 2016 23:25
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Not Understanding 0C4-03B

I would like to convert a Data space to use a Memory Chunk and 64 Bit
Addressing.
Program is invoked in AMODE 31 and RMODE ANY .
When I try to move some control information to the beginning of the memory
chunk I incur a 0C4-03B Abend .
*                                                                  
         SAM64                        Switch To 64 Bit Mode        
         LG    G1,ORIGIN64            Get Starting Address         
         LG    G1,50(,G1)             Position Past Starting Address

         LAY   R2,HDR64               Header Description           
         LLGTR G2,G2                  Ensure G2 has a good address 
         MVC   00(HDR64#,G1),00(R2)   Transfer Header Descripton   
         SAM31                        Return To 31 Bit Mode        
*                                                                  
The MVC instruction abends with an 0c4 - 03B .
.
Can someone on this list explain why I am Abending ,,,, And explain how to
properly correct it.
What exactly am I doing incorrectly
.
.
.
Here is a snipet of code preceding the move.
.

*                                   Use z/Architecture Instructions  
         SYSSTATE AMODE64=YES,ARCHLVL=2                              
*                                                                    
         XGR   G0,G0                   G0 = 0                        
         IARV64 REQUEST=GETSTOR,                                     
               SEGMENTS=SEGMENTS,                                    
               GUARDLOC=HIGH,                                        
               GUARDSIZE=GRDSIZE,                                    
               ORIGIN=ORIGIN64,                                      
               COND=YES,                                             
               FPROT=NO,                                             
               USERTKN=NO_USERTKN,                                   
               TTOKEN=NO_TTOKEN,                                     
               RETCODE=RETCD64,RSNCODE=RSNCD64,                      
               MF=(E,IARV64L,COMPLETE)                               
*                                                                    



         STM   R15,R0,ZRETCODES       Save Return & Reason Code 
*                                                               
         SYSSTATE AMODE64=NO,ARCHLVL=2                          
*                                                               
         BRAS  R14,EXAMINE_RESPONSE                             


*                                                                  
         SAM64                        Switch To 64 Bit Mode        
         LG    G1,ORIGIN64            Get Starting Address         
         LG    G1,50(,G1)             Get Starting Address         
         LARL  R2,HDR64               Header Description           
         LAY   R2,HDR64               Header Description           
         LLGTR G2,G2                  Ensure G2 has a good address 
         MVC   00(HDR64#,G1),00(R2)   Transfer Header Descripton   
         SAM31                        Return To 31 Bit Mode        
*                                                                  
*                                                    
         DS  0AD          .IARV64 Alignment          
SEGMENTS DC  FD'01'       .IARV64 Segments           
ORIGIN64 DC  AD(0)        .IARV64 Origin Address     
HIGH64   DC  AD(0)        .IARV64 High End Address   
         DC  AD(0)        .Reserved               

 
.
.
Paul D'Angelo
*
*


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