I just re-ran a test on our z15 machine and got interesting numbers. The $MVC
was reasonably linear from start to finish. The MVCL has a big jump from 2K to
4K, but was also reasonably linear outside of that jump. It never caught up to
the $MVC implementation.
TEST TYPE = BASE CODE
CPU TIME USED= 0.003873
TEST TYPE = 1K 4 MVC
CPU TIME USED= 0.171274
TEST TYPE = 1K $MVC
CPU TIME USED= 0.183642
TEST TYPE = 1K MVCL
CPU TIME USED= 0.345227
TEST TYPE = 2K $MVC
CPU TIME USED= 0.357314
TEST TYPE = 2K MVCL
CPU TIME USED= 0.509385
TEST TYPE = 4K $MVC
CPU TIME USED= 0.704173
TEST TYPE = 4K MVCL
CPU TIME USED= 2.790247
TEST TYPE = 8K $MVC
CPU TIME USED= 1.426892
TEST TYPE = 8K MVCL
CPU TIME USED= 5.480536
TEST TYPE = 32K $MVC
CPU TIME USED= 5.835773
TEST TYPE = 32K MVCL
CPU TIME USED= 21.734112
TEST TYPE = 64K $MVC
CPU TIME USED= 12.278130
TEST TYPE = 64K MVCL
CPU TIME USED= 43.380435
TEST TYPE = 128K $MVC
CPU TIME USED= 54.570900
TEST TYPE = 128K MVCL
CPU TIME USED= 86.739562
All the iterations used this basic set of instructions.
*
* TEST 1K $MVC
*
SPACE ,
L R9,REPEATCOUNT DO IT 100,000 TIMES
TIMEUSED STORADR=STARTIME,CPU=TOD,LINKAGE=SYSTEM
LOOP1A DS 0H
L R3,POOLADDR GET FROM ADDRESS
L R4,TOADDR GET TO ADDR
L R5,=A(1024) MOVE 1K BYTES
$MVC (R4),(R3),(R5) MOVE IT
AHI R3,1024
AHI R4,1024
BCT R9,LOOP1A LOOP THE NEEDED NUMBER OF TIMES
TIMEUSED STORADR=ENDTIME,CPU=TOD,LINKAGE=SYSTEM
SPACE 3
LA R1,=CL12'1K $MVC'
BAL R14,TIMEOUT
*
* TEST 1K MVCL
*
SPACE ,
L R9,REPEATCOUNT DO IT 100,000 TIMES
TIMEUSED STORADR=STARTIME,CPU=TOD,LINKAGE=SYSTEM
LOOP2 DS 0H
L R2,POOLADDR GET FROM ADDRESS
L R3,=F'1024'
L R4,TOADDR GET TO ADDR
L R5,=F'1024'
MVCL R4,R2 MOVE IT
BCT R9,LOOP2 LOOP THE NEEDED NUMBER OF TIMES
TIMEUSED STORADR=ENDTIME,CPU=TOD,LINKAGE=SYSTEM
SPACE 3
LA R1,=CL12'1K MVCL'
BAL R14,TIMEOUT
The REPEATCOUNT value is 10,000,000
Both POOLADDR and TOADDR areas are 256K in size, so they both should be on page
boundaries.
Chris Blaicher
Technical Architect
Precisely.com
-----Original Message-----
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of Charles Mills
Sent: Tuesday, October 20, 2020 1:57 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Conditional MVCL macro?
This message originated Externally. Use proper judgement and caution with
attachments, links, or responses.
Right.
I should have said "an interruptibility that is visible to the surrounding
assembler instructions via the CC."
Charles
-----Original Message-----
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU]
On Behalf Of Seymour J Metz
Sent: Tuesday, October 20, 2020 10:52 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Conditional MVCL macro?
MVCL is, and always has been, interruptible.
