I don’t believe the paging implications would be any different from an XC.
Sent from my iPhone > On Apr 14, 2022, at 1:26 PM, Paul Gilmartin > <00000014e0e4a59b-dmarc-requ...@listserv.uga.edu> wrote: > > On Apr 14, 2022, at 11:06:09, Tom Harper wrote: >> >> IMHO, the next instruction to add to z/Architecture would be an instruction >> to clear storage to zeros. >> > Would that cause a Lot of paging I/O? Would it be better to mark all pages as > invalid, to be cleared automatically when referenced, if ever? > > That would be an O/S function, not hardware. > > -- > gil -------------------------------------------------------------------------------- This e-mail message, including any attachments, appended messages and the information contained therein, is for the sole use of the intended recipient(s). If you are not an intended recipient or have otherwise received this email message in error, any use, dissemination, distribution, review, storage or copying of this e-mail message and the information contained therein is strictly prohibited. If you are not an intended recipient, please contact the sender by reply e-mail and destroy all copies of this email message and do not otherwise utilize or retain this email message or any or all of the information contained therein. Although this email message and any attachments or appended messages are believed to be free of any virus or other defect that might affect any computer system into which it is received and opened, it is the responsibility of the recipient to ensure that it is virus free and no responsibility is accepted by the sender for any loss or damage arising in any way from its opening or use.
