What are CLCL, MVCL and friends, chopped liver? R0 is perfectly valid and is used to address storage when specified, except when the associated length is zero.
-- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר ________________________________________ From: IBM Mainframe Assembler List <[email protected]> on behalf of Steve Smith <[email protected]> Sent: Tuesday, September 2, 2025 10:27 PM To: [email protected] <[email protected]> Subject: Re: Using (0) to suppress alignment checks in HLASM External Message: Use Caution Well, I dispute that. In most instructions, 0 in an R field has nothing to do with register 0. It explicitly means *no* register is used, and the value of 0 is. It's just solipsistic to say the machine "considers" register 0 to be 0. The language in the PoOp is more like you cannot use register 0 for addressing in most cases. And as far as I can tell, you can't use access register 0 for anything other than volatile temporary storage. sas On Tue, Sep 2, 2025 at 1:37 PM Tony Harminc <[email protected]> wrote: > On Tue, 2 Sept 2025 at 13:05, Steve Smith < > [email protected]> wrote: > > Is there such a thing as an implicit index register? ;-) > > > > Yes, there is. All RX instructions have an index register - it's not in any > sense optional at the machine code level - if you don't explicitly provide > one in the assembler language then the assembler will generate the > instruction using 0. (And of course register 0 when used as an index is > deemed to have the value 0.) It's extremely common for RX instructions to > be used in contexts where no index register is needed. > > But I'm sure you know all this. Now if you had asked "is there such a thing > as specifying an implicit index register?", then that would have a > different answer. ;-) > > Tony H. >
