>From reading the description, I think there are only two possibilities >relating to an 0C4 (access exception):
If an access exception has occurred and the exception PSW still points to the RP instruction (start or end) then processing could not have reached the point where it retrieves second operand values and stores them in the register and PSW, as the last check which may produce an access exception is fetching the whole second operand. In that case, it seems that the base register for the second operand should still have its original value. Otherwise, if the PSW does not point to the start or end of the RP instruction, then the exception is not on the RP itself. Jonathan Scott -----Original Message----- From: IBM Mainframe Assembler List <[email protected]> On Behalf Of Robert Crawford Sent: 17 October 2025 20:00 To: [email protected] Subject: Re: Resume Program (RP) >From your code I'm inferring that the halfwords following the RP instruction >give the offsets from the address in R15 to the values for updating the PSW, >general register and access register, depending on the bit settings, of >course. In your example the contents of R15 would be replaced by whatever's in XTRAP_GREG+15*4. In my dump R15 is zero which, if I'm right about how the instruction works, is not an error. I'll have to see if I can find R15's original value to make sure everything is consistent. Thank you very much for your example. It helped me eliminate a lot of red herrings.
