Hello! There is a discrepancy between MadWifi (specifically the open sourced HAL) and ath5k regarding the meaning some bits in the interrupt status register 2.
>From MadWifi, file ath_hal/ar5212/ar5212reg.h: #define AR_ISR_S2_MCABT 0x00010000 /* Master cycle abort interrupt */ #define AR_ISR_S2_SSERR 0x00020000 /* SERR interrupt */ #define AR_ISR_S2_DPERR 0x00040000 /* PCI bus parity error */ >From ath5k, file drivers/net/wireless/ath/ath5k/reg.h: #define AR5K_SISR2_MCABT 0x00100000 /* Master Cycle Abort */ #define AR5K_SISR2_SSERR 0x00200000 /* Signaled System Error */ #define AR5K_SISR2_DPERR 0x00400000 /* Bus parity error */ The values in ath5k can be traced all the way to ar5k (http://www.openbsd.org/cgi-bin/cvsweb/~checkout~/src/sys/dev/ic/ar5212reg.h) My impression is that the values in MadWifi are correct. Users report actually getting MCABT with the MadWifi value (0x10000) in the madwifi-users list. Both MadWifi and ath9k add a new bit that would conflict with DPERR: #define AR_ISR_S2_CST 0x00400000 /* Carrier sense timeout */ While it's possible for AR5416 to redefine some bits, it's much more likely that DPERR has always been 0x40000, and 0x400000 was reserved. It's possible that the ar5k authors copied the value of MCABT from that for 5210, where MCABT is indeed 0x100000, but in the primary interrupt status resister, not in ISR2. -- Regards, Pavel Roskin _______________________________________________ ath5k-devel mailing list ath5k-devel@lists.ath5k.org https://lists.ath5k.org/mailman/listinfo/ath5k-devel
