On Wed, Aug 12, 2009 at 12:57 PM, Luis R. Rodriguez<lrodrig...@atheros.com> wrote: > This matches ath9k, providing consistency when reading both drivers. > > Signed-off-by: Luis R. Rodriguez <lrodrig...@atheros.com> > --- > drivers/net/wireless/ath/ath5k/base.c | 4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/wireless/ath/ath5k/base.c > b/drivers/net/wireless/ath/ath5k/base.c > index 63c2b57..2b3cf39 100644 > --- a/drivers/net/wireless/ath/ath5k/base.c > +++ b/drivers/net/wireless/ath/ath5k/base.c > @@ -471,7 +471,7 @@ ath5k_pci_probe(struct pci_dev *pdev, > * DMA to work so force a reasonable value here if it > * comes up zero. > */ > - csz = L1_CACHE_BYTES / sizeof(u32); > + csz = L1_CACHE_BYTES >> 2; > pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
I'm not sure it's better, although the whole thing seems bogus to me. Is there really a modern machine where PCI cache line size should only be four bytes? -- Bob Copeland %% www.bobcopeland.com _______________________________________________ ath5k-devel mailing list ath5k-devel@lists.ath5k.org https://lists.ath5k.org/mailman/listinfo/ath5k-devel
