Hello,

While investigating ways to disable CCA on a AR5212, I observed what may be
a couple typos in ath5k/reg.h (in the 2.6.35 kernel version at least):

#define AR5K_DIAG_SW_RX_CLEAR_HIGH      0x0010000       /* Force RX Clear
high
#define AR5K_DIAG_SW_IGNORE_CARR_SENSE  0x0020000       /* Ignore virtual
carri
#define AR5K_DIAG_SW_CHANEL_IDLE_HIGH   0x0040000       /* Force channel
idle h
#define AR5K_DIAG_SW_PHEAR_ME           0x0080000       /* ??? */

Is there a zero missing at the end?  If not, then these seem to conflict
with these other register bit definitions for the diag register:

#define AR5K_DIAG_SW_DIS_SEQ_INC        0x00040000      /* Disable seqnum
incre
#define AR5K_DIAG_SW_FRAME_NV0_5210     0x00080000
#define AR5K_DIAG_SW_FRAME_NV0_5211     0x00020000      /* Accept frames of
non

It would appear either one or the other set of register definitions is
incorrect, and my inclination is the ones containing only 7 hex digits would
be more likely.  That also appears to be a weird spelling of channel
(_CHANEL_IDLE_HIGH).

Interestingly, by adding the zero at the end so these match the values
various researchers messing with CCA on Madwifi are using, I've observed
that it doesn't appear to be possible to set the diag register to 0x00400000
to force channel idle high.  Writing that value to the diag register, then
reading the diag register comes back 0x00000000 and no effect on CCA
behavior is observed.  However, writing 0x00200000 to the diag register
reads back as 0x00200000 (and does appear to affect CCA, although it also
hoses the receiver's sensitivity for some reason), so my code for setting it
appears correct.  This either means the AR5212 chipset doesn't really have
that bit in the diag register, or 0x00400000 isn't the correct value for
AR5K_DIAG_SW_CHANEL_IDLE_HIGH either.

If anyone has actually succeeded in setting the CHANEL_IDLE_HIGH bit in the
diag register, where you using the 7 digit values above or the apparently
correct 8 digit value with the missing 0 added at the end?  And on which
chipset?

Cheers,
 -Ryan

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