While 32 KHz sleep clock might provide some power saving benefits,
it is also a major source of stability issues, on OpenWrt it produced
some reproducible data bus errors on register accesses on several
different MIPS platforms.
All the Atheros drivers that I can find do not enable this feature,
so it makes sense to leave it disabled in ath5k as well.
Signed-off-by: Felix Fietkau <n...@openwrt.org>
---
drivers/net/wireless/ath/ath5k/reset.c | 9 ---------
1 files changed, 0 insertions(+), 9 deletions(-)
diff --git a/drivers/net/wireless/ath/ath5k/reset.c
b/drivers/net/wireless/ath/ath5k/reset.c
index 55276ce..192c0cb 100644
--- a/drivers/net/wireless/ath/ath5k/reset.c
+++ b/drivers/net/wireless/ath/ath5k/reset.c
@@ -1285,15 +1285,6 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum
nl80211_iftype op_mode,
*/
ath5k_hw_dma_init(ah);
-
- /* Enable 32KHz clock function for AR5212+ chips
- * Set clocks to 32KHz operation and use an
- * external 32KHz crystal when sleeping if one
- * exists */
- if (ah->ah_version == AR5K_AR5212 &&
- op_mode != NL80211_IFTYPE_AP)
- ath5k_hw_set_sleep_clock(ah, true);
-
/*
* Disable beacons and reset the TSF
*/
--
1.7.3.2
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