Daniel Smith wrote: > as I understand the explanation it was that a typically > Root Bridge reset is not supposed to occur until later in the > initialization. In this case, the version of AMI that was on this > board did a reset at power-on and then the required one later. This > first reset interferes with serial eeprom loader and causes it to stop > in the middle of initialization. So when the second reset comes along > the cards do not properly enumerate on the bus properly and you end up > with cards in the reported state. The fix the manufacturer did was to > remove the first Root Bridge reset from the BIOS code, after that our > cards would initialize and enumerate onto the bus properly.
Peter Stuge wrote: > What *exactly* is meant by "PCI bus reset" here? So it's PCIe and not PCI. This is an important distinction. I should have figured from the AR93xx. >From Daniel's description above, it seems that the hardware has a limitation in that it must not be reset more than once. That seems like not so reliable PCIe IP, as long as the issue really is well understood, but I'm not sure? I would really like to hear the exact details about what the hardware requires. //Peter _______________________________________________ ath9k-devel mailing list ath9k-devel@lists.ath9k.org https://lists.ath9k.org/mailman/listinfo/ath9k-devel
