Remove register table abstraction layer.
Use direct defines for ar988x.
Signed-off-by: Janusz Dziedzic <janusz.dzied...@tieto.com>
---
drivers/net/wireless/ath/ath10k/Makefile | 4 +-
drivers/net/wireless/ath/ath10k/ar9888_regtable.c | 167 -----------------
drivers/net/wireless/ath/ath10k/ar9888_regtable.h | 26 ---
drivers/net/wireless/ath/ath10k/ar9888def.h | 3 +
drivers/net/wireless/ath/ath10k/ce.c | 1 -
drivers/net/wireless/ath/ath10k/ce.h | 6 +-
drivers/net/wireless/ath/ath10k/core.h | 1 -
drivers/net/wireless/ath/ath10k/pci.c | 179 +++++++++---------
drivers/net/wireless/ath/ath10k/pci.h | 9 +-
drivers/net/wireless/ath/ath10k/regtable.c | 43 -----
drivers/net/wireless/ath/ath10k/regtable.h | 206 ---------------------
11 files changed, 97 insertions(+), 548 deletions(-)
delete mode 100644 drivers/net/wireless/ath/ath10k/ar9888_regtable.c
delete mode 100644 drivers/net/wireless/ath/ath10k/ar9888_regtable.h
delete mode 100644 drivers/net/wireless/ath/ath10k/regtable.c
delete mode 100644 drivers/net/wireless/ath/ath10k/regtable.h
diff --git a/drivers/net/wireless/ath/ath10k/Makefile
b/drivers/net/wireless/ath/ath10k/Makefile
index efd8798..a4179f4 100644
--- a/drivers/net/wireless/ath/ath10k/Makefile
+++ b/drivers/net/wireless/ath/ath10k/Makefile
@@ -14,9 +14,7 @@ ath10k_core-$(CONFIG_ATH10K_TRACING) += trace.o
obj-$(CONFIG_ATH10K_PCI) += ath10k_pci.o
ath10k_pci-y += pci.o \
- ce.o \
- regtable.o \
- ar9888_regtable.o
+ ce.o
# for tracing framework to find trace.h
CFLAGS_trace.o := -I$(src)
diff --git a/drivers/net/wireless/ath/ath10k/ar9888_regtable.c
b/drivers/net/wireless/ath/ath10k/ar9888_regtable.c
deleted file mode 100644
index 5e0b25a..0000000
--- a/drivers/net/wireless/ath/ath10k/ar9888_regtable.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * Copyright (c) 2005-2011 Atheros Communications Inc.
- * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include "ar9888_regtable.h"
-#include "ar9888def.h"
-
-/* AR9888_V1 hostdef, targetdef structures */
-static struct targetdef ar9888_target_def = {
- .D_RTC_SOC_BASE_ADDRESS = RTC_SOC_BASE_ADDRESS,
- .D_RTC_WMAC_BASE_ADDRESS = RTC_WMAC_BASE_ADDRESS,
- .D_SYSTEM_SLEEP_OFFSET = WLAN_SYSTEM_SLEEP_OFFSET,
- .D_WLAN_SYSTEM_SLEEP_OFFSET = WLAN_SYSTEM_SLEEP_OFFSET,
- .D_WLAN_SYSTEM_SLEEP_DISABLE_LSB = WLAN_SYSTEM_SLEEP_DISABLE_LSB,
- .D_WLAN_SYSTEM_SLEEP_DISABLE_MASK = WLAN_SYSTEM_SLEEP_DISABLE_MASK,
- .D_CLOCK_CONTROL_OFFSET = CLOCK_CONTROL_OFFSET,
- .D_CLOCK_CONTROL_SI0_CLK_MASK = CLOCK_CONTROL_SI0_CLK_MASK,
- .D_RESET_CONTROL_OFFSET = SOC_RESET_CONTROL_OFFSET,
- .D_RESET_CONTROL_MBOX_RST_MASK = RESET_CONTROL_MBOX_RST_MASK,
- .D_RESET_CONTROL_SI0_RST_MASK = RESET_CONTROL_SI0_RST_MASK,
- .D_WLAN_RESET_CONTROL_OFFSET = WLAN_RESET_CONTROL_OFFSET,
- .D_WLAN_RESET_CONTROL_COLD_RST_MASK =
WLAN_RESET_CONTROL_COLD_RST_MASK,
- .D_WLAN_RESET_CONTROL_WARM_RST_MASK =
WLAN_RESET_CONTROL_WARM_RST_MASK,
- .D_GPIO_BASE_ADDRESS = GPIO_BASE_ADDRESS,
- .D_GPIO_PIN0_OFFSET = GPIO_PIN0_OFFSET,
- .D_GPIO_PIN1_OFFSET = GPIO_PIN1_OFFSET,
- .D_GPIO_PIN0_CONFIG_MASK = GPIO_PIN0_CONFIG_MASK,
- .D_GPIO_PIN1_CONFIG_MASK = GPIO_PIN1_CONFIG_MASK,
- .D_SI_CONFIG_BIDIR_OD_DATA_LSB = SI_CONFIG_BIDIR_OD_DATA_LSB,
- .D_SI_CONFIG_BIDIR_OD_DATA_MASK = SI_CONFIG_BIDIR_OD_DATA_MASK,
- .D_SI_CONFIG_I2C_LSB = SI_CONFIG_I2C_LSB,
- .D_SI_CONFIG_I2C_MASK = SI_CONFIG_I2C_MASK,
- .D_SI_CONFIG_POS_SAMPLE_LSB = SI_CONFIG_POS_SAMPLE_LSB,
- .D_SI_CONFIG_POS_SAMPLE_MASK = SI_CONFIG_POS_SAMPLE_MASK,
- .D_SI_CONFIG_INACTIVE_CLK_LSB = SI_CONFIG_INACTIVE_CLK_LSB,
- .D_SI_CONFIG_INACTIVE_CLK_MASK = SI_CONFIG_INACTIVE_CLK_MASK,
- .D_SI_CONFIG_INACTIVE_DATA_LSB = SI_CONFIG_INACTIVE_DATA_LSB,
- .D_SI_CONFIG_INACTIVE_DATA_MASK = SI_CONFIG_INACTIVE_DATA_MASK,
- .D_SI_CONFIG_DIVIDER_LSB = SI_CONFIG_DIVIDER_LSB,
- .D_SI_CONFIG_DIVIDER_MASK = SI_CONFIG_DIVIDER_MASK,
- .D_SI_BASE_ADDRESS = SI_BASE_ADDRESS,
- .D_SI_CONFIG_OFFSET = SI_CONFIG_OFFSET,
- .D_SI_TX_DATA0_OFFSET = SI_TX_DATA0_OFFSET,
- .D_SI_TX_DATA1_OFFSET = SI_TX_DATA1_OFFSET,
- .D_SI_RX_DATA0_OFFSET = SI_RX_DATA0_OFFSET,
- .D_SI_RX_DATA1_OFFSET = SI_RX_DATA1_OFFSET,
- .D_SI_CS_OFFSET = SI_CS_OFFSET,
- .D_SI_CS_DONE_ERR_MASK = SI_CS_DONE_ERR_MASK,
- .D_SI_CS_DONE_INT_MASK = SI_CS_DONE_INT_MASK,
- .D_SI_CS_START_LSB = SI_CS_START_LSB,
- .D_SI_CS_START_MASK = SI_CS_START_MASK,
- .D_SI_CS_RX_CNT_LSB = SI_CS_RX_CNT_LSB,
- .D_SI_CS_RX_CNT_MASK = SI_CS_RX_CNT_MASK,
- .D_SI_CS_TX_CNT_LSB = SI_CS_TX_CNT_LSB,
- .D_SI_CS_TX_CNT_MASK = SI_CS_TX_CNT_MASK,
- .D_BOARD_DATA_SZ = MY_TARGET_BOARD_DATA_SZ,
- .D_BOARD_EXT_DATA_SZ = MY_TARGET_BOARD_EXT_DATA_SZ,
- .D_MBOX_BASE_ADDRESS = MBOX_BASE_ADDRESS,
- .D_LOCAL_SCRATCH_OFFSET = LOCAL_SCRATCH_OFFSET,
- .D_CPU_CLOCK_OFFSET = CPU_CLOCK_OFFSET,
- .D_LPO_CAL_OFFSET = LPO_CAL_OFFSET,
- .D_GPIO_PIN10_OFFSET = GPIO_PIN10_OFFSET,
- .D_GPIO_PIN11_OFFSET = GPIO_PIN11_OFFSET,
- .D_GPIO_PIN12_OFFSET = GPIO_PIN12_OFFSET,
- .D_GPIO_PIN13_OFFSET = GPIO_PIN13_OFFSET,
- .D_CLOCK_GPIO_OFFSET = CLOCK_GPIO_OFFSET,
- .D_CPU_CLOCK_STANDARD_LSB = CPU_CLOCK_STANDARD_LSB,
- .D_CPU_CLOCK_STANDARD_MASK = CPU_CLOCK_STANDARD_MASK,
- .D_LPO_CAL_ENABLE_LSB = LPO_CAL_ENABLE_LSB,
- .D_LPO_CAL_ENABLE_MASK = LPO_CAL_ENABLE_MASK,
- .D_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = CLOCK_GPIO_BT_CLK_OUT_EN_LSB,
- .D_CLOCK_GPIO_BT_CLK_OUT_EN_MASK = CLOCK_GPIO_BT_CLK_OUT_EN_MASK,
- .D_ANALOG_INTF_BASE_ADDRESS = ANALOG_INTF_BASE_ADDRESS,
- .D_WLAN_MAC_BASE_ADDRESS = WLAN_MAC_BASE_ADDRESS,
- .D_CE0_BASE_ADDRESS = CE0_BASE_ADDRESS,
- .D_CE1_BASE_ADDRESS = CE1_BASE_ADDRESS,
- .D_FW_INDICATOR_ADDRESS = FW_INDICATOR_ADDRESS,
- .D_DRAM_BASE_ADDRESS = DRAM_BASE_ADDRESS,
- .D_SOC_CORE_BASE_ADDRESS = SOC_CORE_BASE_ADDRESS,
- .D_CORE_CTRL_ADDRESS = CORE_CTRL_ADDRESS,
- .D_CE_COUNT = CE_COUNT,
- .D_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
- .D_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
- .D_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
- .D_MSI_ASSIGN_CE_MAX = MSI_ASSIGN_CE_MAX,
- .D_PCIE_INTR_ENABLE_ADDRESS = PCIE_INTR_ENABLE_ADDRESS,
- .D_PCIE_INTR_CLR_ADDRESS = PCIE_INTR_CLR_ADDRESS,
- .D_PCIE_INTR_FIRMWARE_MASK = PCIE_INTR_FIRMWARE_MASK,
- .D_PCIE_INTR_CE_MASK_ALL = PCIE_INTR_CE_MASK_ALL,
- .D_CORE_CTRL_CPU_INTR_MASK = CORE_CTRL_CPU_INTR_MASK,
- .D_CE_WRAPPER_BASE_ADDRESS = CE_WRAPPER_BASE_ADDRESS,
-};
-
-struct targetdef *ar9888_get_target_tbl(void)
-{
- return &ar9888_target_def;
-}
-
-static struct hostdef ar9888_host_def = {
- .D_INT_STATUS_ENABLE_ERROR_LSB =
INT_STATUS_ENABLE_ERROR_LSB,
- .D_INT_STATUS_ENABLE_ERROR_MASK =
INT_STATUS_ENABLE_ERROR_MASK,
- .D_INT_STATUS_ENABLE_CPU_LSB =
INT_STATUS_ENABLE_CPU_LSB,
- .D_INT_STATUS_ENABLE_CPU_MASK =
INT_STATUS_ENABLE_CPU_MASK,
- .D_INT_STATUS_ENABLE_COUNTER_LSB =
INT_STATUS_ENABLE_COUNTER_LSB,
- .D_INT_STATUS_ENABLE_COUNTER_MASK =
INT_STATUS_ENABLE_COUNTER_MASK,
- .D_INT_STATUS_ENABLE_MBOX_DATA_LSB =
INT_STATUS_ENABLE_MBOX_DATA_LSB,
- .D_INT_STATUS_ENABLE_MBOX_DATA_MASK =
INT_STATUS_ENABLE_MBOX_DATA_MASK,
- .D_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB =
ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB,
- .D_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK =
ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK,
- .D_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB =
ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB,
- .D_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK =
ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK,
- .D_COUNTER_INT_STATUS_ENABLE_BIT_LSB =
COUNTER_INT_STATUS_ENABLE_BIT_LSB,
- .D_COUNTER_INT_STATUS_ENABLE_BIT_MASK =
COUNTER_INT_STATUS_ENABLE_BIT_MASK,
- .D_INT_STATUS_ENABLE_ADDRESS =
INT_STATUS_ENABLE_ADDRESS,
- .D_CPU_INT_STATUS_ENABLE_BIT_LSB =
CPU_INT_STATUS_ENABLE_BIT_LSB,
- .D_CPU_INT_STATUS_ENABLE_BIT_MASK =
CPU_INT_STATUS_ENABLE_BIT_MASK,
- .D_HOST_INT_STATUS_ADDRESS = HOST_INT_STATUS_ADDRESS,
- .D_CPU_INT_STATUS_ADDRESS = CPU_INT_STATUS_ADDRESS,
- .D_ERROR_INT_STATUS_ADDRESS =
ERROR_INT_STATUS_ADDRESS,
- .D_ERROR_INT_STATUS_WAKEUP_MASK =
ERROR_INT_STATUS_WAKEUP_MASK,
- .D_ERROR_INT_STATUS_WAKEUP_LSB =
ERROR_INT_STATUS_WAKEUP_LSB,
- .D_ERROR_INT_STATUS_RX_UNDERFLOW_MASK =
ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
- .D_ERROR_INT_STATUS_RX_UNDERFLOW_LSB =
ERROR_INT_STATUS_RX_UNDERFLOW_LSB,
- .D_ERROR_INT_STATUS_TX_OVERFLOW_MASK =
ERROR_INT_STATUS_TX_OVERFLOW_MASK,
- .D_ERROR_INT_STATUS_TX_OVERFLOW_LSB =
ERROR_INT_STATUS_TX_OVERFLOW_LSB,
- .D_COUNT_DEC_ADDRESS = COUNT_DEC_ADDRESS,
- .D_HOST_INT_STATUS_CPU_MASK =
HOST_INT_STATUS_CPU_MASK,
- .D_HOST_INT_STATUS_CPU_LSB = HOST_INT_STATUS_CPU_LSB,
- .D_HOST_INT_STATUS_ERROR_MASK =
HOST_INT_STATUS_ERROR_MASK,
- .D_HOST_INT_STATUS_ERROR_LSB =
HOST_INT_STATUS_ERROR_LSB,
- .D_HOST_INT_STATUS_COUNTER_MASK =
HOST_INT_STATUS_COUNTER_MASK,
- .D_HOST_INT_STATUS_COUNTER_LSB =
HOST_INT_STATUS_COUNTER_LSB,
- .D_RX_LOOKAHEAD_VALID_ADDRESS =
RX_LOOKAHEAD_VALID_ADDRESS,
- .D_WINDOW_DATA_ADDRESS = WINDOW_DATA_ADDRESS,
- .D_WINDOW_READ_ADDR_ADDRESS =
WINDOW_READ_ADDR_ADDRESS,
- .D_WINDOW_WRITE_ADDR_ADDRESS =
WINDOW_WRITE_ADDR_ADDRESS,
- .D_SOC_GLOBAL_RESET_ADDRESS =
SOC_GLOBAL_RESET_ADDRESS,
- .D_RTC_STATE_ADDRESS = RTC_STATE_ADDRESS,
- .D_RTC_STATE_COLD_RESET_MASK =
RTC_STATE_COLD_RESET_MASK,
- .D_PCIE_LOCAL_BASE_ADDRESS = PCIE_LOCAL_BASE_ADDRESS,
- .D_PCIE_SOC_WAKE_RESET = PCIE_SOC_WAKE_RESET,
- .D_PCIE_SOC_WAKE_ADDRESS = PCIE_SOC_WAKE_ADDRESS,
- .D_PCIE_SOC_WAKE_V_MASK = PCIE_SOC_WAKE_V_MASK,
- .D_RTC_STATE_V_MASK = RTC_STATE_V_MASK,
- .D_RTC_STATE_V_LSB = RTC_STATE_V_LSB,
- .D_FW_IND_EVENT_PENDING = FW_IND_EVENT_PENDING,
- .D_FW_IND_INITIALIZED = FW_IND_INITIALIZED,
- .D_RTC_STATE_V_ON = RTC_STATE_V_ON,
-};
-
-struct hostdef *ar9888_get_host_tbl(void)
-{
- return &ar9888_host_def;
-}
diff --git a/drivers/net/wireless/ath/ath10k/ar9888_regtable.h
b/drivers/net/wireless/ath/ath10k/ar9888_regtable.h
deleted file mode 100644
index 9ccafec..0000000
--- a/drivers/net/wireless/ath/ath10k/ar9888_regtable.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2005-2011 Atheros Communications Inc.
- * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _AR9888_REGTABLE_H_
-#define _AR9888_REGTABLE_H_
-
-#include "regtable.h"
-
-struct targetdef *ar9888_get_target_tbl(void);
-struct hostdef *ar9888_get_host_tbl(void);
-
-#endif /* _AR9888_REGTABLE_H_ */
diff --git a/drivers/net/wireless/ath/ath10k/ar9888def.h
b/drivers/net/wireless/ath/ath10k/ar9888def.h
index 4df8d0d..85e9265 100644
--- a/drivers/net/wireless/ath/ath10k/ar9888def.h
+++ b/drivers/net/wireless/ath/ath10k/ar9888def.h
@@ -231,4 +231,7 @@
#define MY_TARGET_BOARD_DATA_SZ AR9888_BOARD_DATA_SZ
#define MY_TARGET_BOARD_EXT_DATA_SZ AR9888_BOARD_EXT_DATA_SZ
+#define RTC_STATE_V_GET(x) \
+ (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
+
#endif /* __ATH10K_AR9888DEF_H__ */
diff --git a/drivers/net/wireless/ath/ath10k/ce.c
b/drivers/net/wireless/ath/ath10k/ce.c
index 4c29857..d5351a3 100644
--- a/drivers/net/wireless/ath/ath10k/ce.c
+++ b/drivers/net/wireless/ath/ath10k/ce.c
@@ -19,7 +19,6 @@
#include "pci.h"
#include "ce.h"
#include "debug.h"
-#include "regtable.h"
/*
* Support for Copy Engine hardware, which is mainly used for
diff --git a/drivers/net/wireless/ath/ath10k/ce.h
b/drivers/net/wireless/ath/ath10k/ce.h
index 8beb606..084b997 100644
--- a/drivers/net/wireless/ath/ath10k/ce.h
+++ b/drivers/net/wireless/ath/ath10k/ce.h
@@ -474,8 +474,8 @@ struct ce_attr {
#define CE_BASE_ADDRESS(ar, ce_id) \
- (CE0_BASE_ADDRESS_T((ar)) + \
- ((CE1_BASE_ADDRESS_T((ar))-CE0_BASE_ADDRESS_T((ar)))*(ce_id)))
+ (CE0_BASE_ADDRESS + \
+ (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS)*(ce_id))
#define CE_SRC_RING_WRITE_IDX_SET(ar, targid, ce_ctrl_addr, n) \
TARGET_WRITE((ar), (targid), (ce_ctrl_addr) + SR_WR_INDEX_ADDRESS, (n))
@@ -609,7 +609,7 @@ struct ce_attr {
#define CE_INTERRUPT_SUMMARY(ar, targid) \
CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \
- TARGET_READ((targid), CE_WRAPPER_BASE_ADDRESS_T((ar)) + \
+ TARGET_READ((targid), CE_WRAPPER_BASE_ADDRESS + \
CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS))
#endif /* _CE_H_ */
diff --git a/drivers/net/wireless/ath/ath10k/core.h
b/drivers/net/wireless/ath/ath10k/core.h
index 4e19264..ccba50b 100644
--- a/drivers/net/wireless/ath/ath10k/core.h
+++ b/drivers/net/wireless/ath/ath10k/core.h
@@ -26,7 +26,6 @@
#include "htc.h"
#include "hw.h"
#include "targaddrs.h"
-#include "regtable.h"
#include "wmi.h"
#include "../ath.h"
#include "../regd.h"
diff --git a/drivers/net/wireless/ath/ath10k/pci.c
b/drivers/net/wireless/ath/ath10k/pci.c
index 278fa65..b59c3e8 100644
--- a/drivers/net/wireless/ath/ath10k/pci.c
+++ b/drivers/net/wireless/ath/ath10k/pci.c
@@ -22,7 +22,6 @@
#include "core.h"
#include "debug.h"
-#include "regtable.h"
#include "targaddrs.h"
#include "bmi.h"
@@ -121,7 +120,7 @@ static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32
address, u8 *data,
* register read fn but preserve the multi word read capability of
* this fn
*/
- if (address < DRAM_BASE_ADDRESS_T(ar)) {
+ if (address < DRAM_BASE_ADDRESS) {
if ((address & 0x3) || ((dma_addr_t)data & 0x3))
return -EIO;
@@ -250,7 +249,7 @@ done:
static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address, u32
*data)
{
/* Assume range doesn't cross this boundary */
- if (address >= DRAM_BASE_ADDRESS_T(ar))
+ if (address >= DRAM_BASE_ADDRESS)
return ath10k_pci_diag_read_mem(ar, address, (u8 *)data,
sizeof(u32));
else {
@@ -404,7 +403,7 @@ static int ath10k_pci_diag_write_access(struct ath10k *ar,
u32 address,
u32 data)
{
/* Assume range doesn't cross this boundary */
- if (address >= DRAM_BASE_ADDRESS_T(ar)) {
+ if (address >= DRAM_BASE_ADDRESS) {
u32 data_buf = data;
return ath10k_pci_diag_write_mem(ar, address, (u8 *) &data_buf,
sizeof(u32));
@@ -426,9 +425,9 @@ static bool ath10k_pci_target_is_awake(struct ath10k *ar)
{
void __iomem *mem = ath10k_pci_priv(ar)->mem;
u32 val;
- val = ioread32(mem + PCIE_LOCAL_BASE_ADDRESS_T(ar) +
- RTC_STATE_ADDRESS_T(ar));
- return (RTC_STATE_V_GET(ar, val) == RTC_STATE_V_ON_T(ar));
+ val = ioread32(mem + PCIE_LOCAL_BASE_ADDRESS +
+ RTC_STATE_ADDRESS);
+ return (RTC_STATE_V_GET(val) == RTC_STATE_V_ON);
}
static void ath10k_pci_wait_for_target_to_awake(struct ath10k *ar)
@@ -455,8 +454,8 @@ void ath10k_pci_wake(struct ath10k *ar)
if (atomic_read(&ar_pci->keep_awake_count) == 0) {
/* Force AWAKE */
- iowrite32(PCIE_SOC_WAKE_V_MASK_T(ar),
- pci_addr + PCIE_LOCAL_BASE_ADDRESS_T(ar) +
PCIE_SOC_WAKE_ADDRESS_T(ar));
+ iowrite32(PCIE_SOC_WAKE_V_MASK,
+ pci_addr + PCIE_LOCAL_BASE_ADDRESS +
PCIE_SOC_WAKE_ADDRESS);
}
atomic_inc(&ar_pci->keep_awake_count);
@@ -494,8 +493,8 @@ void ath10k_pci_sleep(struct ath10k *ar)
if (atomic_dec_and_test(&ar_pci->keep_awake_count)) {
/* Allow sleep */
ar_pci->verified_awake = false;
- iowrite32(PCIE_SOC_WAKE_RESET_T(ar),
- pci_addr + PCIE_LOCAL_BASE_ADDRESS_T(ar) +
PCIE_SOC_WAKE_ADDRESS_T(ar));
+ iowrite32(PCIE_SOC_WAKE_RESET,
+ pci_addr + PCIE_LOCAL_BASE_ADDRESS +
PCIE_SOC_WAKE_ADDRESS);
}
}
@@ -841,7 +840,7 @@ static void ath10k_pci_stop_ce(struct ath10k *ar)
/* Cancel the pending tasklet */
tasklet_kill(&ar_pci->intr_tq);
- for (i = 0; i < CE_COUNT_T(ar); i++)
+ for (i = 0; i < CE_COUNT; i++)
tasklet_kill(&ar_pci->pipe_info[i].intr);
/* Mark pending completions as aborted, so that upper layers free up
@@ -1465,8 +1464,8 @@ static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
int ret;
u32 core_ctrl;
- ret = ath10k_pci_diag_read_access(ar, SOC_CORE_BASE_ADDRESS_T(ar) |
- CORE_CTRL_ADDRESS_T(ar),
+ ret = ath10k_pci_diag_read_access(ar, SOC_CORE_BASE_ADDRESS |
+ CORE_CTRL_ADDRESS,
&core_ctrl);
if (ret) {
ath10k_warn("Unable to read core ctrl\n");
@@ -1474,10 +1473,10 @@ static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
}
/* A_INUM_FIRMWARE interrupt to Target CPU */
- core_ctrl |= CORE_CTRL_CPU_INTR_MASK_T(ar);
+ core_ctrl |= CORE_CTRL_CPU_INTR_MASK;
- ret = ath10k_pci_diag_write_access(ar, SOC_CORE_BASE_ADDRESS_T(ar) |
- CORE_CTRL_ADDRESS_T(ar),
+ ret = ath10k_pci_diag_write_access(ar, SOC_CORE_BASE_ADDRESS |
+ CORE_CTRL_ADDRESS,
core_ctrl);
if (ret)
ath10k_warn("Unable to set interrupt mask\n");
@@ -1681,7 +1680,7 @@ static int ath10k_pci_probe_device(struct ath10k *ar)
int ret;
atomic_set(&ar_pci->keep_awake_count, 0);
- ar_pci->fw_indicator_address = FW_INDICATOR_ADDRESS_T(ar);
+ ar_pci->fw_indicator_address = FW_INDICATOR_ADDRESS;
if (ath10k_target_ps)
ath10k_dbg(ATH10K_DBG_PCI, "on-chip power save enabled\n");
@@ -1723,10 +1722,10 @@ static void ath10k_pci_fw_interrupt_handler(struct
ath10k *ar)
fw_indicator_address = ar_pci->fw_indicator_address;
fw_indicator = TARGET_READ(targid, fw_indicator_address);
- if (fw_indicator & FW_IND_EVENT_PENDING_T(ar)) {
+ if (fw_indicator & FW_IND_EVENT_PENDING) {
/* ACK: clear Target-side pending event */
TARGET_WRITE(ar, targid, fw_indicator_address,
- fw_indicator & ~FW_IND_EVENT_PENDING_T(ar));
+ fw_indicator & ~FW_IND_EVENT_PENDING);
ath10k_pci_sleep(ar);
if (ar_pci->started)
@@ -1778,7 +1777,7 @@ static irqreturn_t ath10k_pci_per_engine_handler(int irq,
void *arg)
{
struct ath10k *ar = arg;
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
- int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL_T(ar);
+ int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL;
if (ce_id < 0 || ce_id > ARRAY_SIZE(ar_pci->pipe_info)) {
ath10k_warn("%s: unexpected/invalid irq %d ce_id %d\n",
@@ -1824,19 +1823,19 @@ static irqreturn_t ath10k_pci_interrupt_handler(int
irq, void *arg)
* really cleared.
*/
iowrite32(0, ar_pci->mem +
- (SOC_CORE_BASE_ADDRESS_T(ar) |
- PCIE_INTR_ENABLE_ADDRESS_T(ar)));
- iowrite32(PCIE_INTR_FIRMWARE_MASK_T(ar) |
- PCIE_INTR_CE_MASK_ALL_T(ar),
- ar_pci->mem + (SOC_CORE_BASE_ADDRESS_T(ar) |
- PCIE_INTR_CLR_ADDRESS_T(ar)));
+ (SOC_CORE_BASE_ADDRESS |
+ PCIE_INTR_ENABLE_ADDRESS));
+ iowrite32(PCIE_INTR_FIRMWARE_MASK |
+ PCIE_INTR_CE_MASK_ALL,
+ ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
+ PCIE_INTR_CLR_ADDRESS));
/*
* IMPORTANT: this extra read transaction is required to
* flush the posted write buffer.
*/
(void) ioread32(ar_pci->mem +
- (SOC_CORE_BASE_ADDRESS_T(ar) |
- PCIE_INTR_ENABLE_ADDRESS_T(ar)));
+ (SOC_CORE_BASE_ADDRESS |
+ PCIE_INTR_ENABLE_ADDRESS));
}
tasklet_schedule(&ar_pci->intr_tq);
@@ -1854,17 +1853,17 @@ static void ath10k_pci_tasklet(unsigned long data)
if (ar_pci->num_msi_intrs == 0) {
/* Enable Legacy PCI line interrupts */
- iowrite32(PCIE_INTR_FIRMWARE_MASK_T(ar) |
- PCIE_INTR_CE_MASK_ALL_T(ar),
- ar_pci->mem + (SOC_CORE_BASE_ADDRESS_T(ar) |
- PCIE_INTR_ENABLE_ADDRESS_T(ar)));
+ iowrite32(PCIE_INTR_FIRMWARE_MASK |
+ PCIE_INTR_CE_MASK_ALL,
+ ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
+ PCIE_INTR_ENABLE_ADDRESS));
/*
* IMPORTANT: this extra read transaction is required to
* flush the posted write buffer
*/
(void) ioread32(ar_pci->mem +
- (SOC_CORE_BASE_ADDRESS_T(ar) |
- PCIE_INTR_ENABLE_ADDRESS_T(ar)));
+ (SOC_CORE_BASE_ADDRESS |
+ PCIE_INTR_ENABLE_ADDRESS));
}
}
@@ -1889,29 +1888,29 @@ static int ath10k_pci_reset_target(struct ath10k *ar)
int wait_limit = 300; /* 3 sec */
while (wait_limit-- &&
- !(ioread32(ar_pci->mem + FW_INDICATOR_ADDRESS_T(ar)) &
- FW_IND_INITIALIZED_T(ar))) {
+ !(ioread32(ar_pci->mem + FW_INDICATOR_ADDRESS) &
+ FW_IND_INITIALIZED)) {
if (ar_pci->num_msi_intrs == 0)
/* Fix potential race by repeating CORE_BASE writes */
- iowrite32(PCIE_INTR_FIRMWARE_MASK_T(ar) |
- PCIE_INTR_CE_MASK_ALL_T(ar),
- ar_pci->mem + (SOC_CORE_BASE_ADDRESS_T(ar) |
-
PCIE_INTR_ENABLE_ADDRESS_T(ar)));
+ iowrite32(PCIE_INTR_FIRMWARE_MASK |
+ PCIE_INTR_CE_MASK_ALL,
+ ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
+ PCIE_INTR_ENABLE_ADDRESS));
mdelay(10);
}
if (wait_limit < 0) {
ath10k_err("Target stalled\n");
- iowrite32(PCIE_SOC_WAKE_RESET_T(ar),
- ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS_T(ar) +
- PCIE_SOC_WAKE_ADDRESS_T(ar));
+ iowrite32(PCIE_SOC_WAKE_RESET,
+ ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
+ PCIE_SOC_WAKE_ADDRESS);
return -EIO;
}
- iowrite32(PCIE_SOC_WAKE_RESET_T(ar),
- ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS_T(ar) +
- PCIE_SOC_WAKE_ADDRESS_T(ar));
+ iowrite32(PCIE_SOC_WAKE_RESET,
+ ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
+ PCIE_SOC_WAKE_ADDRESS);
return 0;
}
@@ -1920,14 +1919,14 @@ static int ath10k_pci_configure(struct ath10k *ar)
{
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
int ret = 0;
- int num_msi_desired = MSI_NUM_REQUEST_T(ar);
+ int num_msi_desired = MSI_NUM_REQUEST;
int i;
tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long) ar);
tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
(unsigned long) ar);
- for (i = 0; i < CE_COUNT_T(ar); i++) {
+ for (i = 0; i < CE_COUNT; i++) {
ar_pci->pipe_info[i].ar_pci = ar_pci;
tasklet_init(&ar_pci->pipe_info[i].intr,
ath10k_pci_ce_tasklet,
@@ -1958,7 +1957,7 @@ static int ath10k_pci_configure(struct ath10k *ar)
if (ret == 0) {
ar_pci->num_msi_intrs = num_msi_desired;
ret = request_irq(ar_pci->pdev->irq +
- MSI_ASSIGN_FW_T(ar),
+ MSI_ASSIGN_FW,
ath10k_pci_msi_fw_handler,
IRQF_SHARED,
"ath10k_pci",
@@ -1968,8 +1967,8 @@ static int ath10k_pci_configure(struct ath10k *ar)
goto err_intr;
}
- for (i = MSI_ASSIGN_CE_INITIAL_T(ar);
- i <= MSI_ASSIGN_CE_MAX_T(ar); i++) {
+ for (i = MSI_ASSIGN_CE_INITIAL;
+ i <= MSI_ASSIGN_CE_MAX; i++) {
ret = request_irq(ar_pci->pdev->irq + i,
ath10k_pci_per_engine_handler,
IRQF_SHARED,
@@ -2037,9 +2036,9 @@ static int ath10k_pci_configure(struct ath10k *ar)
* Make sure to wake the Target before enabling Legacy
* Interrupt.
*/
- iowrite32(PCIE_SOC_WAKE_V_MASK_T(ar),
- ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS_T(ar) +
- PCIE_SOC_WAKE_ADDRESS_T(ar));
+ iowrite32(PCIE_SOC_WAKE_V_MASK,
+ ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
+ PCIE_SOC_WAKE_ADDRESS);
ath10k_pci_wait_for_target_to_awake(ar);
@@ -2051,25 +2050,25 @@ static int ath10k_pci_configure(struct ath10k *ar)
* For now, fix the race by repeating the write in below
* synchronization checking.
*/
- iowrite32(PCIE_INTR_FIRMWARE_MASK_T(ar) |
- PCIE_INTR_CE_MASK_ALL_T(ar),
- ar_pci->mem + (SOC_CORE_BASE_ADDRESS_T(ar) |
- PCIE_INTR_ENABLE_ADDRESS_T(ar)));
- iowrite32(PCIE_SOC_WAKE_RESET_T(ar),
- ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS_T(ar) +
- PCIE_SOC_WAKE_ADDRESS_T(ar));
+ iowrite32(PCIE_INTR_FIRMWARE_MASK |
+ PCIE_INTR_CE_MASK_ALL,
+ ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
+ PCIE_INTR_ENABLE_ADDRESS));
+ iowrite32(PCIE_SOC_WAKE_RESET,
+ ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
+ PCIE_SOC_WAKE_ADDRESS);
}
ar_pci->num_msi_intrs = num_msi_desired;
- ar_pci->ce_count = CE_COUNT_T(ar);
+ ar_pci->ce_count = CE_COUNT;
/*
* Synchronization point: Wait for Target to finish initialization
* before we proceed.
*/
- iowrite32(PCIE_SOC_WAKE_V_MASK_T(ar),
- ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS_T(ar) +
- PCIE_SOC_WAKE_ADDRESS_T(ar));
+ iowrite32(PCIE_SOC_WAKE_V_MASK,
+ ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
+ PCIE_SOC_WAKE_ADDRESS);
ath10k_pci_wait_for_target_to_awake(ar);
@@ -2110,14 +2109,14 @@ static void ath10k_pci_device_reset(struct ath10k_pci
*ar_pci)
int i;
u32 val;
- if (!SOC_GLOBAL_RESET_ADDRESS_T(ar))
+ if (!SOC_GLOBAL_RESET_ADDRESS)
return;
if (!mem)
return;
- A_PCIE_LOCAL_REG_WRITE(mem, PCIE_SOC_WAKE_ADDRESS_T(ar),
- PCIE_SOC_WAKE_V_MASK_T(ar));
+ A_PCIE_LOCAL_REG_WRITE(mem, PCIE_SOC_WAKE_ADDRESS,
+ PCIE_SOC_WAKE_V_MASK);
for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
if (ath10k_pci_target_is_awake(ar))
break;
@@ -2125,30 +2124,30 @@ static void ath10k_pci_device_reset(struct ath10k_pci
*ar_pci)
}
/* Put Target, including PCIe, into RESET. */
- val = A_PCIE_LOCAL_REG_READ(mem, SOC_GLOBAL_RESET_ADDRESS_T(ar));
+ val = A_PCIE_LOCAL_REG_READ(mem, SOC_GLOBAL_RESET_ADDRESS);
val |= 1;
- A_PCIE_LOCAL_REG_WRITE(mem, SOC_GLOBAL_RESET_ADDRESS_T(ar), val);
+ A_PCIE_LOCAL_REG_WRITE(mem, SOC_GLOBAL_RESET_ADDRESS, val);
for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
- if (A_PCIE_LOCAL_REG_READ(mem, RTC_STATE_ADDRESS_T(ar)) &
- RTC_STATE_COLD_RESET_MASK_T(ar))
+ if (A_PCIE_LOCAL_REG_READ(mem, RTC_STATE_ADDRESS) &
+ RTC_STATE_COLD_RESET_MASK)
break;
msleep(1);
}
/* Pull Target, including PCIe, out of RESET. */
val &= ~1;
- A_PCIE_LOCAL_REG_WRITE(mem, SOC_GLOBAL_RESET_ADDRESS_T(ar), val);
+ A_PCIE_LOCAL_REG_WRITE(mem, SOC_GLOBAL_RESET_ADDRESS, val);
for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
- if (!(A_PCIE_LOCAL_REG_READ(mem, RTC_STATE_ADDRESS_T(ar)) &
- RTC_STATE_COLD_RESET_MASK_T(ar)))
+ if (!(A_PCIE_LOCAL_REG_READ(mem, RTC_STATE_ADDRESS) &
+ RTC_STATE_COLD_RESET_MASK))
break;
msleep(1);
}
- A_PCIE_LOCAL_REG_WRITE(mem, PCIE_SOC_WAKE_ADDRESS_T(ar),
- PCIE_SOC_WAKE_RESET_T(ar));
+ A_PCIE_LOCAL_REG_WRITE(mem, PCIE_SOC_WAKE_ADDRESS,
+ PCIE_SOC_WAKE_RESET);
}
static void ath10k_pci_dump_features(struct ath10k_pci *ar_pci)
@@ -2295,14 +2294,6 @@ retry:
ar_pci->cacheline_sz = dma_get_cache_alignment();
/*
- * Attach Target register table. This is needed early on --
- * even before BMI -- since PCI and HIF initialization (and BMI init)
- * directly access Target registers (e.g. CE registers).
- */
- ath10k_register_host_reg_table(ar, hif_type);
- ath10k_register_target_reg_table(ar, target_type);
-
- /*
* Verify that the Target was started cleanly.
*
* The case where this is most likely is with an AUX-powered
@@ -2313,17 +2304,17 @@ retry:
* We try to catch that here in order to reset the Target and
* retry the probe.
*/
- iowrite32(PCIE_SOC_WAKE_V_MASK_T(ar),
- mem + PCIE_LOCAL_BASE_ADDRESS_T(ar) +
- PCIE_SOC_WAKE_ADDRESS_T(ar));
+ iowrite32(PCIE_SOC_WAKE_V_MASK,
+ mem + PCIE_LOCAL_BASE_ADDRESS +
+ PCIE_SOC_WAKE_ADDRESS);
ath10k_pci_wait_for_target_to_awake(ar);
- fw_indicator = ioread32(mem + FW_INDICATOR_ADDRESS_T(ar));
- iowrite32(PCIE_SOC_WAKE_RESET_T(ar),
- mem + PCIE_LOCAL_BASE_ADDRESS_T(ar) +
- PCIE_SOC_WAKE_ADDRESS_T(ar));
+ fw_indicator = ioread32(mem + FW_INDICATOR_ADDRESS);
+ iowrite32(PCIE_SOC_WAKE_RESET,
+ mem + PCIE_LOCAL_BASE_ADDRESS +
+ PCIE_SOC_WAKE_ADDRESS);
- if (fw_indicator & FW_IND_INITIALIZED_T(ar)) {
+ if (fw_indicator & FW_IND_INITIALIZED) {
probe_again++;
ath10k_err("target is in an unknown state. "
"resetting (attempt %d).\n", probe_again);
diff --git a/drivers/net/wireless/ath/ath10k/pci.h
b/drivers/net/wireless/ath/ath10k/pci.h
index a3b5e88..8c77d90 100644
--- a/drivers/net/wireless/ath/ath10k/pci.h
+++ b/drivers/net/wireless/ath/ath10k/pci.h
@@ -20,6 +20,7 @@
#include <linux/interrupt.h>
+#include "ar9888def.h"
#include "ce.h"
/*
@@ -229,11 +230,11 @@ static inline struct ath10k_pci *ath10k_pci_priv(struct
ath10k *ar)
}
#define A_PCIE_LOCAL_REG_READ(mem, addr) \
- ioread32((mem) + PCIE_LOCAL_BASE_ADDRESS_T(ar) + (u32)(addr))
+ ioread32((mem) + PCIE_LOCAL_BASE_ADDRESS + (u32)(addr))
#define A_PCIE_LOCAL_REG_WRITE(mem, addr, val) \
iowrite32((val), \
- ((mem) + PCIE_LOCAL_BASE_ADDRESS_T(ar) + (u32)(addr)))
+ ((mem) + PCIE_LOCAL_BASE_ADDRESS + (u32)(addr)))
#define ATH_PCI_RESET_WAIT_MAX 10 /* Ms */
#define PCIE_WAKE_TIMEOUT 5000 /* 5Ms */
@@ -251,8 +252,8 @@ static inline struct ath10k_pci *ath10k_pci_priv(struct
ath10k *ar)
* for this device; but that's not guaranteed.
*/
#define TARG_CPU_SPACE_TO_CE_SPACE(ar, pci_addr, addr) \
- (((ioread32((pci_addr)+(SOC_CORE_BASE_ADDRESS_T((ar))| \
- CORE_CTRL_ADDRESS_T((ar)))) & 0x7ff) << 21) | \
+ (((ioread32((pci_addr)+(SOC_CORE_BASE_ADDRESS| \
+ CORE_CTRL_ADDRESS)) & 0x7ff) << 21) | \
0x100000 | ((addr) & 0xfffff))
/* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
diff --git a/drivers/net/wireless/ath/ath10k/regtable.c
b/drivers/net/wireless/ath/ath10k/regtable.c
deleted file mode 100644
index e5c985d..0000000
--- a/drivers/net/wireless/ath/ath10k/regtable.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2005-2011 Atheros Communications Inc.
- * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include "hif.h"
-#include "core.h"
-
-#include "ar9888_regtable.h"
-
-void ath10k_register_target_reg_table(struct ath10k *ar, u32 target_type)
-{
- switch (target_type) {
- case TARGET_TYPE_AR9888:
- ar->targetdef = ar9888_get_target_tbl();
- break;
- default:
- break;
- }
-}
-
-void ath10k_register_host_reg_table(struct ath10k *ar, u32 hif_type)
-{
- switch (hif_type) {
- case HIF_TYPE_AR9888:
- ar->hostdef = ar9888_get_host_tbl();
- break;
- default:
- break;
- }
-}
diff --git a/drivers/net/wireless/ath/ath10k/regtable.h
b/drivers/net/wireless/ath/ath10k/regtable.h
deleted file mode 100644
index 4a7b728..0000000
--- a/drivers/net/wireless/ath/ath10k/regtable.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * Copyright (c) 2005-2011 Atheros Communications Inc.
- * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef __REGTABLE_H__
-#define __REGTABLE_H__
-
-#include <linux/types.h>
-
-/* TARGET REGISTERS TABLE */
-struct targetdef {
- u32 D_RTC_SOC_BASE_ADDRESS;
- u32 D_RTC_WMAC_BASE_ADDRESS;
- u32 D_SYSTEM_SLEEP_OFFSET;
- u32 D_WLAN_SYSTEM_SLEEP_OFFSET;
- u32 D_WLAN_SYSTEM_SLEEP_DISABLE_LSB;
- u32 D_WLAN_SYSTEM_SLEEP_DISABLE_MASK;
- u32 D_CLOCK_CONTROL_OFFSET;
- u32 D_CLOCK_CONTROL_SI0_CLK_MASK;
- u32 D_RESET_CONTROL_OFFSET;
- u32 D_RESET_CONTROL_MBOX_RST_MASK;
- u32 D_RESET_CONTROL_SI0_RST_MASK;
- u32 D_WLAN_RESET_CONTROL_OFFSET;
- u32 D_WLAN_RESET_CONTROL_COLD_RST_MASK;
- u32 D_WLAN_RESET_CONTROL_WARM_RST_MASK;
- u32 D_GPIO_BASE_ADDRESS;
- u32 D_GPIO_PIN0_OFFSET;
- u32 D_GPIO_PIN1_OFFSET;
- u32 D_GPIO_PIN0_CONFIG_MASK;
- u32 D_GPIO_PIN1_CONFIG_MASK;
- u32 D_SI_CONFIG_BIDIR_OD_DATA_LSB;
- u32 D_SI_CONFIG_BIDIR_OD_DATA_MASK;
- u32 D_SI_CONFIG_I2C_LSB;
- u32 D_SI_CONFIG_I2C_MASK;
- u32 D_SI_CONFIG_POS_SAMPLE_LSB;
- u32 D_SI_CONFIG_POS_SAMPLE_MASK;
- u32 D_SI_CONFIG_INACTIVE_CLK_LSB;
- u32 D_SI_CONFIG_INACTIVE_CLK_MASK;
- u32 D_SI_CONFIG_INACTIVE_DATA_LSB;
- u32 D_SI_CONFIG_INACTIVE_DATA_MASK;
- u32 D_SI_CONFIG_DIVIDER_LSB;
- u32 D_SI_CONFIG_DIVIDER_MASK;
- u32 D_SI_BASE_ADDRESS;
- u32 D_SI_CONFIG_OFFSET;
- u32 D_SI_TX_DATA0_OFFSET;
- u32 D_SI_TX_DATA1_OFFSET;
- u32 D_SI_RX_DATA0_OFFSET;
- u32 D_SI_RX_DATA1_OFFSET;
- u32 D_SI_CS_OFFSET;
- u32 D_SI_CS_DONE_ERR_MASK;
- u32 D_SI_CS_DONE_INT_MASK;
- u32 D_SI_CS_START_LSB;
- u32 D_SI_CS_START_MASK;
- u32 D_SI_CS_RX_CNT_LSB;
- u32 D_SI_CS_RX_CNT_MASK;
- u32 D_SI_CS_TX_CNT_LSB;
- u32 D_SI_CS_TX_CNT_MASK;
- u32 D_BOARD_DATA_SZ;
- u32 D_BOARD_EXT_DATA_SZ;
- u32 D_MBOX_BASE_ADDRESS;
- u32 D_LOCAL_SCRATCH_OFFSET;
- u32 D_CPU_CLOCK_OFFSET;
- u32 D_LPO_CAL_OFFSET;
- u32 D_GPIO_PIN10_OFFSET;
- u32 D_GPIO_PIN11_OFFSET;
- u32 D_GPIO_PIN12_OFFSET;
- u32 D_GPIO_PIN13_OFFSET;
- u32 D_CLOCK_GPIO_OFFSET;
- u32 D_CPU_CLOCK_STANDARD_LSB;
- u32 D_CPU_CLOCK_STANDARD_MASK;
- u32 D_LPO_CAL_ENABLE_LSB;
- u32 D_LPO_CAL_ENABLE_MASK;
- u32 D_CLOCK_GPIO_BT_CLK_OUT_EN_LSB;
- u32 D_CLOCK_GPIO_BT_CLK_OUT_EN_MASK;
- u32 D_ANALOG_INTF_BASE_ADDRESS;
- u32 D_WLAN_MAC_BASE_ADDRESS;
- u32 D_CE0_BASE_ADDRESS;
- u32 D_CE1_BASE_ADDRESS;
- u32 D_FW_INDICATOR_ADDRESS;
- u32 D_DRAM_BASE_ADDRESS;
- u32 D_SOC_CORE_BASE_ADDRESS;
- u32 D_CORE_CTRL_ADDRESS;
- u32 D_CE_COUNT;
- u32 D_MSI_NUM_REQUEST;
- u32 D_MSI_ASSIGN_FW;
- u32 D_MSI_ASSIGN_CE_INITIAL;
- u32 D_MSI_ASSIGN_CE_MAX;
- u32 D_PCIE_INTR_ENABLE_ADDRESS;
- u32 D_PCIE_INTR_CLR_ADDRESS;
- u32 D_PCIE_INTR_FIRMWARE_MASK;
- u32 D_PCIE_INTR_CE_MASK_ALL;
- u32 D_CORE_CTRL_CPU_INTR_MASK;
- u32 D_CE_WRAPPER_BASE_ADDRESS;
-};
-
-
-/* target */
-/* helper macros to fetch registers via ar->targdef */
-#define CE0_BASE_ADDRESS_T(ar) ((ar)->targetdef->D_CE0_BASE_ADDRESS)
-#define CE1_BASE_ADDRESS_T(ar) ((ar)->targetdef->D_CE1_BASE_ADDRESS)
-#define FW_INDICATOR_ADDRESS_T(ar) ((ar)->targetdef->D_FW_INDICATOR_ADDRESS)
-#define DRAM_BASE_ADDRESS_T(ar) ((ar)->targetdef->D_DRAM_BASE_ADDRESS)
-#define SOC_CORE_BASE_ADDRESS_T(ar) ((ar)->targetdef->D_SOC_CORE_BASE_ADDRESS)
-#define CORE_CTRL_ADDRESS_T(ar) ((ar)->targetdef->D_CORE_CTRL_ADDRESS)
-#define CE_COUNT_T(ar) ((ar)->targetdef->D_CE_COUNT)
-#define PCIE_INTR_ENABLE_ADDRESS_T(ar) \
- ((ar)->targetdef->D_PCIE_INTR_ENABLE_ADDRESS)
-#define PCIE_INTR_CLR_ADDRESS_T(ar) ((ar)->targetdef->D_PCIE_INTR_CLR_ADDRESS)
-#define PCIE_INTR_FIRMWARE_MASK_T(ar) \
- ((ar)->targetdef->D_PCIE_INTR_FIRMWARE_MASK)
-#define PCIE_INTR_CE_MASK_ALL_T(ar) ((ar)->targetdef->D_PCIE_INTR_CE_MASK_ALL)
-#define CORE_CTRL_CPU_INTR_MASK_T(ar) \
- ((ar)->targetdef->D_CORE_CTRL_CPU_INTR_MASK)
-#define CE_WRAPPER_BASE_ADDRESS_T(ar) \
- ((ar)->targetdef->D_CE_WRAPPER_BASE_ADDRESS)
-#define MSI_NUM_REQUEST_T(ar) ((ar)->targetdef->D_MSI_NUM_REQUEST)
-#define MSI_ASSIGN_FW_T(ar) ((ar)->targetdef->D_MSI_ASSIGN_FW)
-#define MSI_ASSIGN_CE_INITIAL_T(ar) ((ar)->targetdef->D_MSI_ASSIGN_CE_INITIAL)
-#define MSI_ASSIGN_CE_MAX_T(ar) ((ar)->targetdef->D_MSI_ASSIGN_CE_MAX)
-
-/* HOST REGISTERS TABLE */
-struct hostdef {
- u32 D_INT_STATUS_ENABLE_ERROR_LSB;
- u32 D_INT_STATUS_ENABLE_ERROR_MASK;
- u32 D_INT_STATUS_ENABLE_CPU_LSB;
- u32 D_INT_STATUS_ENABLE_CPU_MASK;
- u32 D_INT_STATUS_ENABLE_COUNTER_LSB;
- u32 D_INT_STATUS_ENABLE_COUNTER_MASK;
- u32 D_INT_STATUS_ENABLE_MBOX_DATA_LSB;
- u32 D_INT_STATUS_ENABLE_MBOX_DATA_MASK;
- u32 D_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB;
- u32 D_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK;
- u32 D_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB;
- u32 D_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK;
- u32 D_COUNTER_INT_STATUS_ENABLE_BIT_LSB;
- u32 D_COUNTER_INT_STATUS_ENABLE_BIT_MASK;
- u32 D_INT_STATUS_ENABLE_ADDRESS;
- u32 D_CPU_INT_STATUS_ENABLE_BIT_LSB;
- u32 D_CPU_INT_STATUS_ENABLE_BIT_MASK;
- u32 D_HOST_INT_STATUS_ADDRESS;
- u32 D_CPU_INT_STATUS_ADDRESS;
- u32 D_ERROR_INT_STATUS_ADDRESS;
- u32 D_ERROR_INT_STATUS_WAKEUP_MASK;
- u32 D_ERROR_INT_STATUS_WAKEUP_LSB;
- u32 D_ERROR_INT_STATUS_RX_UNDERFLOW_MASK;
- u32 D_ERROR_INT_STATUS_RX_UNDERFLOW_LSB;
- u32 D_ERROR_INT_STATUS_TX_OVERFLOW_MASK;
- u32 D_ERROR_INT_STATUS_TX_OVERFLOW_LSB;
- u32 D_COUNT_DEC_ADDRESS;
- u32 D_HOST_INT_STATUS_CPU_MASK;
- u32 D_HOST_INT_STATUS_CPU_LSB;
- u32 D_HOST_INT_STATUS_ERROR_MASK;
- u32 D_HOST_INT_STATUS_ERROR_LSB;
- u32 D_HOST_INT_STATUS_COUNTER_MASK;
- u32 D_HOST_INT_STATUS_COUNTER_LSB;
- u32 D_RX_LOOKAHEAD_VALID_ADDRESS;
- u32 D_WINDOW_DATA_ADDRESS;
- u32 D_WINDOW_READ_ADDR_ADDRESS;
- u32 D_WINDOW_WRITE_ADDR_ADDRESS;
- u32 D_SOC_GLOBAL_RESET_ADDRESS;
- u32 D_RTC_STATE_ADDRESS;
- u32 D_RTC_STATE_COLD_RESET_MASK;
- u32 D_PCIE_LOCAL_BASE_ADDRESS;
- u32 D_PCIE_SOC_WAKE_RESET;
- u32 D_PCIE_SOC_WAKE_ADDRESS;
- u32 D_PCIE_SOC_WAKE_V_MASK;
- u32 D_RTC_STATE_V_MASK;
- u32 D_RTC_STATE_V_LSB;
- u32 D_FW_IND_EVENT_PENDING;
- u32 D_FW_IND_INITIALIZED;
- u32 D_RTC_STATE_V_ON;
-};
-
-/* host */
-#define SOC_GLOBAL_RESET_ADDRESS_T(ar) \
- ((ar)->hostdef->D_SOC_GLOBAL_RESET_ADDRESS)
-#define RTC_STATE_ADDRESS_T(ar) ((ar)->hostdef->D_RTC_STATE_ADDRESS)
-#define RTC_STATE_COLD_RESET_MASK_T(ar) \
- ((ar)->hostdef->D_RTC_STATE_COLD_RESET_MASK)
-#define PCIE_LOCAL_BASE_ADDRESS_T(ar) \
- ((ar)->hostdef->D_PCIE_LOCAL_BASE_ADDRESS)
-#define PCIE_SOC_WAKE_RESET_T(ar) ((ar)->hostdef->D_PCIE_SOC_WAKE_RESET)
-#define PCIE_SOC_WAKE_ADDRESS_T(ar) ((ar)->hostdef->D_PCIE_SOC_WAKE_ADDRESS)
-#define PCIE_SOC_WAKE_V_MASK_T(ar) ((ar)->hostdef->D_PCIE_SOC_WAKE_V_MASK)
-#define RTC_STATE_V_MASK_T(ar) ((ar)->hostdef->D_RTC_STATE_V_MASK)
-#define RTC_STATE_V_LSB_T(ar) ((ar)->hostdef->D_RTC_STATE_V_LSB)
-#define FW_IND_EVENT_PENDING_T(ar) ((ar)->hostdef->D_FW_IND_EVENT_PENDING)
-#define FW_IND_INITIALIZED_T(ar) ((ar)->hostdef->D_FW_IND_INITIALIZED)
-#define RTC_STATE_V_ON_T(ar) ((ar)->hostdef->D_RTC_STATE_V_ON)
-#define RTC_STATE_V_GET(ar, x) \
- (((x) & RTC_STATE_V_MASK_T(ar)) >> RTC_STATE_V_LSB_T(ar))
-
-#endif /* __REGTABLE_H__ */
--
1.7.9.5
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