Skunk Wrote: > CS8412 doesn't, but CS8411 has a built in buffer. The CS8412 uses a > on-chip PLL to recover sender clock data. > > I seem to recall Sean saying the programmable PLL chip (not sure if > it's on the receiver chip or seperate) is part of the key to SB2/3's > low jitter, along with other things.
There are no PLLs in SB2/SB3 for the audio chain [this is a reason why it sounds better than SB1 which had a PLL for the master clock for the 3rd part chip used.] Indeed it has separate crystal oscillators for 44.1 and 48 KHz, specifically to allow this and support multiple sampling frequencies [compare this to certain other computer based products with don't] CS8412 has a single sample buffer, CS8411 buffers a small number of samples. Key point is that they both support 2 modes: 1) output clocked by recovery of clock from the spdif line 2) output clocked by local clock in the DAC In the first case, the internal PLL recovers the clock from the spdif datastream and is used to clock out the data - hence samples are clocked out at the rate they are arriving. In local clock mode, the local clock can run faster/slower than the clock generating the data. In this case either chip will drop or insert a sample. Now the issue that has been learnt over time is that jitter on the conversion clock at the DAC chip is much more noticable than people originally thought. Essentially the issue is that the correct samples reproduced at slightly the wrong instance in time results in distortion which is audible (arguably as bad as slightly the wrong sample reproduced at the correct instance in time) Hence to get the best reproduction you really want a low jitter clock directly connected to the dac chip as this is what is doing the digital to analogue conversion. A crystal oscillator is always going to be lower jitter than a non crystal based PLL - which is essentially a guessing circuit [create a clock, compare it to the incoming one and change it a bit if it is going to fast or too slow] Two box systems which use DACs are hamstrung by spdif as it was designed prior to knowledge of the jitter issue and so make it difficult to extract a precise clock from the data signal due to both the data and clock being encoded together. Hence a PLL is needed to extract data at the receiver chip in the DAC box. Recent dacs have attempted to address this in multiple ways, e.g: 1) Asychronous clocking [just run the DAC with its own clock, make no attempt to sychronise the two and put up with the occasional sample being dropped or repeated on the basis that such errors are less audibly noticable than jitter on the clock] e.g. DDDAC diy dacs (http://www.dddac.de/) 2) Crystal based PLL (VCXO) which is able to produce a low jitter version of the recovered clock as it is based on a crystal oscillator. Note there is no need for a large buffer to do this as as the jitter between the input clock and the conversion clock only equates to fractions of a sample time. E.g. Tentlabs XO-DAC (technical background: http://members.chello.nl/%7em.heijligers/DAChtml/PLL/PLL1.htm) 3) Asychronous resampling - resample the data in the dac to a new sampling rate defined by a local low jitter crystal based oscillator and then use this to clock the dac chip for conversion. This uses an asychronous resampler chip which actually creates new sample values to represent the data at a new data rate. The conversion chip is really doing some clever math to convert between sample values and so is able to absorb an amount of jitter on the input stream as it can assume the input samples were produced at a fixed rate (it does not need them to turn up at exactly this rate). The upside is that the jitter at the conversion chip is low, but the actual sample values are changed as the sampling rate is changed. Now SB2/3 is a one box system so it gets excellent quality for level of the components used by using a low jitter crystal oscillator and connecting this direct to the dac chip without the need for an spdif link. When an external dac is used, as spdif has to be used the questions over how the clock is recovered in the dac and used to clock the D/A conversion all apply... -- Triode ------------------------------------------------------------------------ Triode's Profile: http://forums.slimdevices.com/member.php?userid=17 View this thread: http://forums.slimdevices.com/showthread.php?t=22301 _______________________________________________ audiophiles mailing list audiophiles@lists.slimdevices.com http://lists.slimdevices.com/lists/listinfo/audiophiles
