Thanks for chiming in John. After considering your prior feedback and reading up on synch reclocking I've managed to create a schematic which is attached. Does it look like it might work? The right side (i.e. my external DAC schematic) is fortunately all done. I just need to create a resynch board with the Tent mlck and DFlops and reg psu. The last piece of the puzzle (I'm stumped!) is I know the schematic is missing 1 Dflop that is required to take the SB3 Left Justified Sig and convert it to pure philips I2S (I have tda1541 twin dac chips..though unbalanced). Any guidance on the input, clock and output for this add'l flop? Also, I don't know if I NEED all 4 flops...I read posts by Jocko and Guido stating always better to use only 1 input per flop.
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