Actually I'm using PCM1704 chips, the data stream from the SB3 (its actually left justified not I2S) gets split into the two right justified streams for the 1704s in the FPGA in the DAC box, the two data signals and bclk and wclk are reclocked by single gate flops (TI little logic) driven by the selected low jitter clock, the flops are right next to the DAC chips.
The output stage is a discrete MOSFET IV and buffer design of mine, it runs at fairly high voltage and current, IMO it sounds better than OP-amp or BJT descrete output stages, but is large and produces a fair amount of heat. (I did it this way to get the best linearity out of the MOSFETs, not to "power" the load). This gives considerably lower jitter than feeding the same clock into the FPGA in the SB3 and directly using its outputs. The FPGA adds some jitter to the signals, at about 35ps instead of 8ps for the way I did it. I can hear the difference it makes. Of course putting the low jitter clock in the SB3 and having the FPGA directly driving a very good DAC and output stage will still sound very good, considerably better than what is in there now AND be much simpler than what I did, but hey I was after the best I could do. John S. -- JohnSwenson ------------------------------------------------------------------------ JohnSwenson's Profile: http://forums.slimdevices.com/member.php?userid=5974 View this thread: http://forums.slimdevices.com/showthread.php?t=35642 _______________________________________________ audiophiles mailing list audiophiles@lists.slimdevices.com http://lists.slimdevices.com/lists/listinfo/audiophiles
