Steve Franks <[email protected]> wrote: > This unbuffered > shift register is junk.
Well, SPI is a hardware shift register with no chance for the slave to signal whether it's got the data ready or not. It's well suited to be implemented in a hardware shift register (like in an FPGA or CPLD) but not so well suited to be implemented in a controller that takes its time to prepare the data after asserting the chip select signal. You could try I²C instead since it allows for the slave to extend the timing when being overwhelmed by the master. -- cheers, J"org .-.-. --... ...-- -.. . DL8DTL http://www.sax.de/~joerg/ NIC: JW11-RIPE Never trust an operating system you don't have sources for. ;-) _______________________________________________ AVR-chat mailing list [email protected] http://lists.nongnu.org/mailman/listinfo/avr-chat
