Vincent Trouilliez <[email protected]> wrote: > I would not mind someone confirming this scenario or telling me > otherwise if need be, please ! ;-)
Just get rid of the idea that SFRs (aka. IO registers) behave the same as a standard SRAM cell would. Instead, they simply establish access paths to certain hardware features, and often, the access path when issuing a write operation is something completely different than the path when issuing a read operation. That way, you should simply never assume in the first place (unless it's explicitly explained so in the datasheet) that any data you wrote to a particular SFR could be read back. The most obvious example for that is the UDR register of the USART: writing it will load the transmit buffer (and trigger a transmission if necessary), reading it will read the receive buffer. The FAQ explains why interrupt flags are normally cleared by writing a logical 1 into them: http://www.nongnu.org/avr-libc/user-manual/FAQ.html#faq_intbits The only difference for TWINT (compared to most AVR interrupts) is that it doesn't auto-clear upon entering the ISR. This is because clearing it triggers the next START condition, so by requiring the firmware to explicitly handle that, it's got full control about when the next bus cycle is going to happen. -- cheers, J"org .-.-. --... ...-- -.. . DL8DTL http://www.sax.de/~joerg/ NIC: JW11-RIPE Never trust an operating system you don't have sources for. ;-) _______________________________________________ AVR-chat mailing list [email protected] http://lists.nongnu.org/mailman/listinfo/avr-chat
