> -----Original Message----- > From: [email protected] > [mailto:[email protected]] > On Behalf Of Bob Paddock > Sent: Tuesday, March 31, 2009 10:16 AM > To: [email protected] > Subject: [avr-chat] XMega PDI_DATA and PDI_CLK must be balanced? > > I'm doing a my first design with a XMega, there are sections about > the PDI interface I'm not clear on. In AVR1005 we can read: > > "5.1 Hardware design requirements to make PDI work > > The PDI interface is a synchronous half-duplex UART > interface. The two lines, > PDI_DATA and PDI_CLK, must therefore be balanced. If you > place a strong pull-up > and decoupling cap on the PDI_CLK, which is also the Reset line, the > clock and data > will no longer be synchronized correctly. Therefore, during > development you should > remove any pull-up and decoupling capacitors. This also > applies if using the PDI > interface for in-system programming the XMEGA in production."
Sorry, but to be fair, I'm not a EE. My background is in software engineering. I can't answer these types of questions for you. :-( Your best bet would be to ask [email protected] for clarification, or your local FAE. Eric Weddington _______________________________________________ AVR-chat mailing list [email protected] http://lists.nongnu.org/mailman/listinfo/avr-chat
