On Sun, Apr 28, 2013 at 2:12 AM, Rick Mann <[email protected]> wrote:
> So, I'm sitting here trying to port ChibiOS to XMEGA. It runs well on > something like an ATmega128. I have not looked at ChibiOS so can not speak to that directly. Many RTOS's work by building Task Control Blocks and/or stack frames then 'returning' to code that was never actually called, rather it was jumped to. Typically in the start up phase of the RTOS such TCBs/stack frames are created. > Doesn't it also not re-enable interrupts on MEGA? How can it work on MEGA and > not XMEGA? The XMega, unlike the Mega, has three levels of interrupt priorities. Only the RETI instruction correctly deals with restoring the priorities correctly. To my knowledge there is no way to correctly build a stack frame that the PCMI would correctly use, that it did not create due to the internal hardware of the XMega. Not being able to 'return' to code that was never called removed classes of RTOS's and task managers from being able to work on the XMega. > Does anyone know what differences I might need to look into? As you found RETI vs RET. Not using RETI on the XMega will lead to system crashes, especially with nested interrupt priorities. The PCMI state is not correctly restored by RET. >From the XMega AU Manual: "The PMIC status register contains state information that ensures that the PMIC returns to the correct interrupt level when the RETI (interrupt return) instruction is executed at the end of an interrupt handler. Returning from an interrupt will return the PMIC to the state it had before entering the interrupt. The status register (SREG) is not saved automatically upon an interrupt request. THE RET (SUBROUTINE RETURN) INSTRUCTION CANNOT BE USED WHEN RETURNING FROM THE INTERRUPT HANDLER ROUTINE, AS THIS WILL NOT RETURN THE PMIC TO ITS CORRECT STATE." [Emphases Mine. Hopefully system libraries are written with that in mind!] Also note this in section 2.3 of App. Note AVR1305: "It is important to take into consideration that the Global Interrupt bit (I-bit in SREG) is not cleared when entering an interrupt, as opposed to the single level interrupt system in megaAVR™ microcontrollers. The PMIC contains the mechanism that ensures that interrupts having same level cannot interrupt each other. Please refer to the description of the PMIC STATUS register found in the datasheet for more information." That change could result in unexpected recursive interrupts that crash the stack for code not written for the Xmega when porting from the Mega. -- http://blog.softwaresafety.net/ http://www.designer-iii.com/ http://www.wearablesmartsensors.com/ _______________________________________________ AVR-chat mailing list [email protected] https://lists.nongnu.org/mailman/listinfo/avr-chat
