On 08.11.16 15:55, Britton Kerin wrote: > Having thought about this more I believe the root of the problem is > shown in Fig-1 of the ATMega328P datasheet.
Fig 17-1 on p87, I guess. > When sleeping the clock is stopped, and when idle I think clk is shut > off to the input circuit of 17-1, but in either case pin change > detection can occur, so obviously it isn't happening due to that > circuit. According to Table 14-1, clkIO is active in Idle mode, and pin change wake-up is effective if unmasked. OK, Fig 17-1 only shows the clock as "clk", so the two do not corroborate well. The first paragraph of the "Interrupts" introduction, above figure 17-1 states: >>> Pin change interrupts on PCINT are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. <<< The first sentence confirms the pcint_in_(0) --- (x) pin change interrupts are taken from the AND gates inputting to the OR gate, i.e. a pin change would be detected even if the clock were stopped. There is a 3-clock delay before capture in a PCIFR flag, but IIRC your code does not rely on PCIFR, and the interrupt has already been generated by then, AIUI. Have you tried filling all unused vector table slots with a vector to a third LED blinker, so that if (inexplicably) another interrupt is enabled and occasionally waking the system, you'll know? (It is nearly 20 years now since that scenario caused me some debugging effort.) Erik _______________________________________________ AVR-chat mailing list AVR-chat@nongnu.org https://lists.nongnu.org/mailman/listinfo/avr-chat
