Your code is exactly the same as the C one : when the overflow occur (exactly during the cli instruction), r22=r23=0, but (r24,r25) is not incremented !
-----Original Message----- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Gavin Jackson Sent: Thursday, October 13, 2005 12:08 AM To: Dmitry K.; avr-gcc-list@nongnu.org Subject: RE: [avr-gcc-list] 32-bits time >> Dear All, >> >> I have implemented a 32-bits time information using the code below. >> Timer1 is incremented using internal clock, prescaler=1; SIG_OVERFLOW >> interrupt is used to increment a variable used to complete >> the 16-bits of Timer1. >> >> In fact, the code below have the following problem: if the call is made >> exactly when the counter overflow, TCNT1 (tempL) is equal to zero, but >> hiword_time (tempH) is pending to be incremented, leading to an error >> (time is returning in the past). >> >> Does anybody has a solution ? > >1: lds r22, TCNT1L > lds r23, TCNT1H > lds r24, hiword_time > lds r25, hiword_time + 1 > lds r0, TCNT1L > cp r0, r22 > brne 1b > ret > >This code work if you will use it only with flag 'SREG.I' setting. I don't think this is going to work with the prescaler set to 1. r22 and R0 will always be different by the time you come to doing the cp R0, R22. cli lds r22, TCNT1L lds r23, TCNT1H lds r24, hiword_time lds r25, hiword_time + 1 sei will capture the time the moment the TCNT1L is read. When the low byte of the timer is read, the high byte is latched. By disabling interrupts you prevent the overflow of the timer changing the two bytes that make up your hi_word time variable. Gavin _______________________________________________ AVR-GCC-list mailing list AVR-GCC-list@nongnu.org http://lists.nongnu.org/mailman/listinfo/avr-gcc-list _______________________________________________ AVR-GCC-list mailing list AVR-GCC-list@nongnu.org http://lists.nongnu.org/mailman/listinfo/avr-gcc-list
