On Mon, May 19, 2014 at 10:22 AM, Joerg Wunsch <[email protected]> wrote: > As Bob Paddock wrote: > >> > I do not see where this clock domain synchronization is accounted for >> > in avr/wdt.h wdt_enable(). > > As *I* read it, this synchronization is something that happens > internally to the device, and the SYNCBUSY bit only indicates > whether a synchronization is still pending.
It is internal to the device, true. Simply must wait for the slower clock domain to catch up by stopping the faster domain, so that it is no longer pending. This is standard stuff anytime you cross clock domains. Read just about any RTC datasheet and it comes up. > I wish the datasheet were a little more explicit here about what > user code is expected to do with the SYNCBUSY bit. I took it literally. The clock domains must be synchronized to communicate the enable/disable state between the different registers (state machines?) of the part. I do not remember from three years ago when I originally raised the question, if waiting for SYNCBUSY fixed my random reset or not. I know I did implement it and it did not hurt. Making a test case for something like this is almost impossible because the drifting clock domains make it seem random, when they are not synchronized. _______________________________________________ AVR-libc-dev mailing list [email protected] https://lists.nongnu.org/mailman/listinfo/avr-libc-dev
