2011/3/18 George Kashperko <[email protected]>: > Well, here you are: > 1. PCI hosts with PCI buscores prior rev. 13 (8Kb window) > offset size type description > 0x0000 0x1000 sliding controlled with BAR0_WIN1 register > 0x1000 0x0800 fixed SPROM > 0x1800 0x0400 fixed PCI core (core registers 0x0000 to 0x03FF range) > 0x1C00 0x0400 fixed PCI core (agent registers, 0x0C00 to 0x0FFF range) > > 2. PCI hosts with PCI buscores rev. 13 and above and PCIE with > Chipcommon rev. up to 31 (16Kb window) > offset size type description > 0x0000 0x1000 sliding controlled with BAR0_WIN1 register > 0x1000 0x1000 fixed SPROM > 0x2000 0x1000 fixed PCI core > 0x3000 0x1000 fixed Chipcommon core > > 3. PCIE hosts with Chipcommon rev. 32 and above > offset size type description > 0x0000 0x1000 sliding controlled with BAR0_WIN1 register > 0x1000 0x1000 sliding controlled with BAR0_WIN2 register > 0x2000 0x1000 fixed PCI core > 0x3000 0x1000 fixed Chipcommon core > > As you can see even if PCI_REVISION can't feed us with guaranteed choice > of either of these 3 layouts we can distingiush between them easily like > following: > > if (pci_is_pcie(dev)) { > u32 chipid = ioread32(bar0_base + 0x3000); > if (chipid & 0x10000000) > /* AXI, Chipcommon rev. is 32+ */ > goto win_3_setup; > else > /* SB, Chipcommon rev. is <= 31 */ > goto win_2_setup; > } else { > u32 idhi = ioread32(bar0_base + 0x1C00 + 0x03FC); > if (((idhi & 0x00008FF0) >> 4) == 0x804) > /* PCI core id */ > goto win_1_setup; > else > /* Some crap from SPROM area */ > goto win_2_setup; > } > > Therefore we can setup PCI(e) host windows for backplane access prior to > scanning. > > As for BAR0_WIN[12] registers, they point to physical base address on > backplane that will be mapped into corresponding 0x1000-size window. And > here again registers don't care what exactly you want to see there. Both > the windows can be controlled independently. > > Finally, you might noticed we don't have SPROM in last 3rd layout. Thats > because it is in Chipcommon registers' space. For layouts #1 & #2 BAR0 > range 0x1000 to 0x2000 is either mapped to actual SPROM or to SPROM > shadow in PCI core.
Wohoo, and this is second part of info I really needed, thanks a lot! I think there are mistakes in it, but I just wanted to get the idea of windows. So thanks a lot. As for mistakes: 1) The split is not 1-31 vs. 32-... I believe it is 1-30 vs. 31-... 2) On chipco >= 31 SSB SPROM seems to be 0x800 Maybe sth more... -- Rafał _______________________________________________ b43-dev mailing list [email protected] http://lists.infradead.org/mailman/listinfo/b43-dev
