W dniu 17 lipca 2011 18:40 użytkownik Rafał Miłecki <[email protected]> napisał: > W dniu 17 lipca 2011 12:22 użytkownik Kalle Valo <[email protected]> napisał: >> Rafał Miłecki <[email protected]> writes: >> >>> W dniu 16 lipca 2011 03:14 użytkownik Rafał Miłecki <[email protected]> >>> napisał: >>>> My last hope is to find some magic in PCI config space. >>> >>> After dumping PCI config space ops, I've noticed there are writes to 4 >>> uniq registers: >>> 0x0D ← latency timer (setting to 64) >>> 0x40 ← Disabling RETRY_TIMEOUT register (0x41) >>> 0x80 ← PCI_BAR0_WIN >>> 0xAC ← PCI_BAR0_WIN2 >>> >>> No magic here :( I've no idea what now. I don't see a single >>> difference between b43 and wl. >> >> What about timing? Maybe wl is slower in some cases? > > I've hacked bcma putting mdelay(1) after ever R/W op. It didn't help. > > I've discovered different interesting thing however. Register 0x1E0 is > not ChipCommon specific. It is valid for every core on my boards: > ChipCommon, 80211 and PCIE.
To make it clear: wl set clock and enables PLL on 80211 core. For all the time I misinterpreted wl ops thinking it's performed on CC core. -- Rafał _______________________________________________ b43-dev mailing list [email protected] http://lists.infradead.org/mailman/listinfo/b43-dev
