The rate is not constant as the comment said, but is hclk. The result
was that MII clock was often calculated wrong.
Reported-by: Michael Grzeschik <m.grzesc...@pengutronix.de>
Signed-off-by: Wolfram Sang <w.s...@pengutronix.de>
---
arch/arm/mach-mxs/speed-imx28.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-mxs/speed-imx28.c b/arch/arm/mach-mxs/speed-imx28.c
index df55f64..2cab42d 100644
--- a/arch/arm/mach-mxs/speed-imx28.c
+++ b/arch/arm/mach-mxs/speed-imx28.c
@@ -121,8 +121,7 @@ unsigned imx_get_xtalclk(void)
unsigned imx_get_fecclk(void)
{
- /* this PLL always runs at 50 MHz */
- return 50000000;
+ return imx_get_hclk();
}
--
1.7.10.4
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