From: Fabio Estevam <fabio.este...@freescale.com>
Setup CCM_CCOSR register to provide a CKO1 clock frequency of 16.5 MHz.
CKO1 drives sgtl5000 codec clock on mx6qsabrelite and doing this setup in the
bootloader will allow us to remove a lot of code in
arch/arm/mach-imx/mach-imx6q.c
from the mainline kernel.
Signed-off-by: Fabio Estevam <fabio.este...@freescale.com>
---
.../boards/freescale-mx6-sabrelite/flash_header.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boards/freescale-mx6-sabrelite/flash_header.c
b/arch/arm/boards/freescale-mx6-sabrelite/flash_header.c
index 61d482b..49326e0 100644
--- a/arch/arm/boards/freescale-mx6-sabrelite/flash_header.c
+++ b/arch/arm/boards/freescale-mx6-sabrelite/flash_header.c
@@ -152,6 +152,17 @@ struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DCD(MX6_IOMUXC_BASE_ADDR + 0x018, 0x007f007f),
DCD(MX6_IOMUXC_BASE_ADDR + 0x01c, 0x007f007f),
+
+ /*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en = 1 --> CKO1 enabled
+ * cko1_div = 111 --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+ DCD(MX6_CCM_BASE_ADDR + 0x060, 0x000000fb),
};
#define APP_DEST CONFIG_TEXT_BASE
--
1.7.9.5
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